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公开(公告)号：US12254318B2
公开(公告)日：2025-03-18
申请号：US18143990
申请日：2023-05-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
Abstract: A system determines an original instruction with a first logical register (LR) mapped to a first physical register (PR). The system determines a current instruction with a current LR. A prior instruction is associated with a second LR mapped to a second PR. The system allocates the current LR to a third PR. Responsive to determining that the current and prior instructions are executed in different iterations, the system marks the second PR as not eligible for early release. Responsive to determining that the current LR is previously mapped to the first PR, the allocation comprises a redefinition of the first LR. Responsive to determining that the first PR is eligible for early release and that the current and original instructions are executed in the same or consecutive iterations, the system releases the first PR based upon the redefinition and not the prior instruction completing or the current instruction committing.
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公开(公告)号：US20230315471A1
公开(公告)日：2023-10-05
申请号：US18328099
申请日：2023-06-02
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
CPC classification number: G06F9/3814 , G06F9/30065 , G06F9/321 , G06F9/5016
Abstract: One aspect provides a system for hardware-assisted pre-execution. During operation, the system determines a pre-execution code region comprising one or more instructions. The system increments a global counter upon initiating the one or more instructions. The system issues a first instruction, which involves setting, in a first entry for the first instruction in a data structure, a first prefetch region identifier with a current value of the global counter. Responsive to a head pointer of the data structure reaching the first entry, the system: determines, based on a non-zero value for the first prefetch region identifier, that the first entry is not available to be allocated; and advances the head pointer to a next entry in the data structure, which renders a load associated with the first entry as a non-blocking load. The system resets the global counter upon completing the one or more instructions.
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公开(公告)号：US11687344B2
公开(公告)日：2023-06-27
申请号：US17412200
申请日：2021-08-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
CPC classification number: G06F9/3814 , G06F9/30047 , G06F9/30065 , G06F9/321 , G06F9/38 , G06F9/3802 , G06F9/5016
Abstract: One aspect provides a system for hardware-assisted pre-execution. During operation, the system determines a pre-execution code region comprising one or more instructions. The system increments a global counter upon initiating the one or more instructions. The system issues a first instruction, which involves setting, in a first entry for the first instruction in a data structure, a first prefetch region identifier with a current value of the global counter. Responsive to a head pointer of the data structure reaching the first entry, the system: determines, based on a non-zero value for the first prefetch region identifier, that the first entry is not available to be allocated; and advances the head pointer to a next entry in the data structure, which renders a load associated with the first entry as a non-blocking load. The system resets the global counter upon completing the one or more instructions.
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公开(公告)号：US20240248719A1
公开(公告)日：2024-07-25
申请号：US18143990
申请日：2023-05-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
CPC classification number: G06F9/3013 , G06F9/30058 , G06F9/3861
Abstract: A system determines an original instruction with a first logical register (LR) mapped to a first physical register (PR). The system determines a current instruction with a current LR. A prior instruction is associated with a second LR mapped to a second PR. The system allocates the current LR to a third PR. Responsive to determining that the current and prior instructions are executed in different iterations, the system marks the second PR as not eligible for early release. Responsive to determining that the current LR is previously mapped to the first PR, the allocation comprises a redefinition of the first LR. Responsive to determining that the first PR is eligible for early release and that the current and original instructions are executed in the same or consecutive iterations, the system releases the first PR based upon the redefinition and not the prior instruction completing or the current instruction committing.
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公开(公告)号：US20230061576A1
公开(公告)日：2023-03-02
申请号：US17412200
申请日：2021-08-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
Abstract: One aspect provides a system for hardware-assisted pre-execution. During operation, the system determines a pre-execution code region comprising one or more instructions. The system increments a global counter upon initiating the one or more instructions. The system issues a first instruction, which involves setting, in a first entry for the first instruction in a data structure, a first prefetch region identifier with a current value of the global counter. Responsive to a head pointer of the data structure reaching the first entry, the system: determines, based on a non-zero value for the first prefetch region identifier, that the first entry is not available to be allocated; and advances the head pointer to a next entry in the data structure, which renders a load associated with the first entry as a non-blocking load. The system resets the global counter upon completing the one or more instructions.
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Patent Agency Ranking
公开(公告)号：US12079631B2
公开(公告)日：2024-09-03
申请号：US18328099
申请日：2023-06-02
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
CPC classification number: G06F9/3814 , G06F9/30047 , G06F9/30065 , G06F9/321 , G06F9/38 , G06F9/3802 , G06F9/5016
Abstract: One aspect provides a system for hardware-assisted pre-execution. During operation, the system determines a pre-execution code region comprising one or more instructions. The system increments a global counter upon initiating the one or more instructions. The system issues a first instruction, which involves setting, in a first entry for the first instruction in a data structure, a first prefetch region identifier with a current value of the global counter. Responsive to a head pointer of the data structure reaching the first entry, the system: determines, based on a non-zero value for the first prefetch region identifier, that the first entry is not available to be allocated; and advances the head pointer to a next entry in the data structure, which renders a load associated with the first entry as a non-blocking load. The system resets the global counter upon completing the one or more instructions.
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7.发明公开公开(公告)号：US20230359358A1
公开(公告)日：2023-11-09
申请号：US17662356
申请日：2022-05-06
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Sanyam Mehta
IPC: G06F3/06 , G06F12/0811
CPC classification number: G06F3/0611 , G06F3/0629 , G06F3/0673 , G06F12/0811 , G06F2212/604
Abstract: A process includes determining a memory bandwidth of a processor subsystem corresponding to an execution of an application by the processor subsystem. The process includes determining an average memory latency corresponding to the execution of the application and determining an average occupancy of a miss status handling register queue associated with the execution of the application based on the memory bandwidth and the average memory latency. The process includes, based on the average occupancy of the miss status handling register queue and a capacity of the miss status handling register queue, generating data that represents a recommendation of an optimization to be applied to the application.
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公开(公告)号：US20250155955A1
公开(公告)日：2025-05-15
申请号：US18388573
申请日：2023-11-10
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Anna Yazhi Yue , Torsten Wilde , Sanyam Mehta
IPC: G06F1/329
Abstract: A region-aware power/energy regulation method comprises periodically identifying a region of an application which is currently being executed by a given processor out of a plurality of regions of the application. The method also comprises measuring the instructions per second (IPS) of the given processor during execution of the identified region. The method also comprises determining a compute-boundedness parameter of the identified region based on the measured IPS. The method also comprises determining an optimal frequency for the identified region based on the compute-boundedness parameter thereof, and instructing the given processor to set a frequency of the given processor to the optimal frequency during execution of the identified region.
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公开(公告)号：US11941250B2
公开(公告)日：2024-03-26
申请号：US17662356
申请日：2022-05-06
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Sanyam Mehta
IPC: G06F3/06 , G06F12/0811
CPC classification number: G06F3/0611 , G06F3/0629 , G06F3/0673 , G06F12/0811 , G06F2212/604
Abstract: A process includes determining a memory bandwidth of a processor subsystem corresponding to an execution of an application by the processor subsystem. The process includes determining an average memory latency corresponding to the execution of the application and determining an average occupancy of a miss status handling register queue associated with the execution of the application based on the memory bandwidth and the average memory latency. The process includes, based on the average occupancy of the miss status handling register queue and a capacity of the miss status handling register queue, generating data that represents a recommendation of an optimization to be applied to the application.
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公开(公告)号：US11531544B1
公开(公告)日：2022-12-20
申请号：US17388666
申请日：2021-07-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sanyam Mehta
Abstract: The system creates, in a scheduler data structure, a first entry for a consumer instruction associated with a logical register ID. The first entry includes: a scheduler entry ID; a physical register ID allocated for the logical register ID; a checkpoint ID; one or more scheduler entry IDs for one or more prior producer instructions; and a release field which indicates whether to early release a physical register. The system updates a register alias table entry to include the scheduler entry ID and the checkpoint ID of the consumer instruction. The system receives the scheduler entry ID and a checkpoint ID for a respective prior producer instruction. Responsive to determining that the received checkpoint ID does not match the checkpoint ID associated with the consumer instruction, the system sets a release field to indicate that a physical register is to remain allocated.
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