公开(公告)号：EP2979189A4

公开(公告)日：2016-10-19

申请号：EP13879895

申请日：2013-03-28

Applicant: HEWLETT PACKARD ENTPR DEV LP

Inventor： FARABOSCHI PABLO ,  BOEHM HANS ,  CHAKRABARTI DHRUVA ,  MURALIMANOHAR NAVEEN

IPC: G06F12/0804 ,  G06F3/06

CPC classification number: G06F12/0893 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0679 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/202 ,  G06F2212/60

Abstract: A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory.

Abstract translation: 提供了一种执行存储器操作的方法。 一个或多个处理器可以确定存储在一个或多个处理器的高速缓冲存储器中的数据的至少一部分将被存储在主存储器中。 确定与主存储器中的多个高速缓存行相对应的主存储器的一个或多个地址范围。 识别与一个或多个地址范围中的地址相对应的一组缓存行，使得存储在所识别的集合中的数据可以存储在主存储器中。 对于具有由于该高速缓存线首先被加载到高速缓存存储器而被修改的数据的已识别集合的每个高速缓存行，或者由于先前存储操作，存储在该高速缓存行中的数据被存储在主存储器中。