公开(公告)号：WO2014084836A1

公开(公告)日：2014-06-05

申请号：PCT/US2012/067085

申请日：2012-11-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： KADRI, Rachid M

IPC: G06F11/20 ,  G06F1/00

CPC classification number: G06F11/2033 ,  G06F11/1064 ,  G06F11/2038 ,  G06F11/2043 ,  G06F11/2097 ,  G06F2201/845

Abstract: Examples disclose a multi-core circuit with a primary core associated with a primary portion of cache and a secondary core associated with a secondary portion of the cache. The secondary portion of the cache is redundant to the primary portion of the cache. Further, the examples of the multi-core circuit provide a control circuit to enable the secondary core for operation in response to a fault condition detected at the primary core, wherein the secondary portion of cache is enabled with the secondary core to resume an operation of the primary core.

Abstract translation: 示例公开了具有与高速缓存的主要部分相关联的主核心的多核电路和与高速缓存的次级部分相关联的次级核心。 缓存的次级部分对于高速缓存的主要部分是冗余的。 此外，多核电路的示例提供了控制电路，以使辅助核心能够响应于在主核心处检测到的故障状况而进行操作，其中高速缓存的次级部分能够被辅助核心恢复到 主要核心。