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    SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NON-VOLATILE MEMORY
    4.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NON-VOLATILE MEMORY 审中-公开
    为非易失性存储器提供低延迟读取路径的系统和方法

    公开(公告)号：US20170017544A1

    公开(公告)日：2017-01-19

    申请号：US14963025

    申请日：2015-12-08

    Applicant: HGST Netherlands B.V.

    Inventor： Zvonimir Z. Bandic ,  Kiran Kumar Gunnam ,  Minghai Qin ,  Dejan Vucinic

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/3715

    Abstract: Aspects of the disclosure relate to storage systems for providing low latency read access of a non-volatile memory. One such system includes a non-volatile memory (NVM) configured for read access via a primary data path, a syndrome checker disposed along the primary read data path and configured to check a codeword read from the NVM for errors, an error correction code circuitry disposed outside of the primary data path and, if the codeword is determined to contain an error, configured to determine a location of the error in the codeword, and a queue disposed along the primary read data path. The queue is configured to receive the codeword from the syndrome checker and output the codeword to a host. If the codeword is determined to contain the error, the queue corrects the error based on the determined location of the error from the error correction code circuitry.

    Abstract translation: 本公开的方面涉及用于提供非易失性存储器的低延迟读取访问的存储系统。 一种这样的系统包括被配置用于经由主要数据路径进行读取访问的非易失性存储器（NVM），沿主要读取数据路径布置并被配置为检查从NVM读取的代码字的错误校正码电路 设置在主数据路径之外，并且如果确定码字包含错误，被配置为确定码字中的错误的位置以及沿着主要读取数据路径设置的队列。 队列被配置为从识别器检查器接收码字并将码字输出到主机。 如果码字被确定为包含错误，则队列根据确定的来自纠错码电路的错误位置来校正错误。

    GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING
    5.
    发明申请
    GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING 有权
    使用本地和全球交互的非易失性存储器中随机地址映射的生成

    公开(公告)号：US20170017578A1

    公开(公告)日：2017-01-19

    申请号：US14967169

    申请日：2015-12-11

    Applicant: HGST Netherlands B.V.

    Inventor： Kiran Kumar Gunnam

    IPC: G06F12/10

    CPC classification number: G06F12/1072 ,  G06F8/458 ,  G06F9/52 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2201/825 ,  G06F2212/154 ,  G06F2212/202 ,  G06F2212/608 ,  G06F2212/7201 ,  G06F2212/7211

    Abstract: Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N-G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N-G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N-G) bits.

    Abstract translation: 提供了使用局部和全局交错在非易失性存储器中产生随机地址映射的系统和方法。 用于产生用于非易失性存储器（NVM）的随机地址映射的一种这样的方法涉及识别NVM的物理地址空间中的位数（N），选择要用于的N位的G位 全局交错，其中G小于N，确定要用于本地交织的比特数（NG），使用用于全局交织的映射函数映射G比特，使用交织功能交织（NG）比特， 并且生成包括映射的G位和交错（NG）位的组合映射。

    Systems and methods for offloading processing from a host to storage processing units using an interconnect network
    6.
    发明授权
    Systems and methods for offloading processing from a host to storage processing units using an interconnect network 有权

    公开(公告)号：US10095445B2

    公开(公告)日：2018-10-09

    申请号：US15084333

    申请日：2016-03-29

    Applicant: HGST Netherlands B.V.

    Inventor： Arup De ,  Kiran Kumar Gunnam

    IPC: G06F9/46 ,  G06F3/06 ,  G06F9/50

    Abstract: Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such system includes a host having a processing task, a plurality of storage processing units (SPUs), a host interface configured to enable communications between the host and each of the plurality of SPUs, and an interconnection network coupled to at least two of the plurality of SPUs, where the host is configured to command at least one of the plurality of SPUs to perform the processing task, and command the interconnection network to couple two or more of the plurality of SPUs.

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