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    Control equipments, control systems, and data generation methods
    1.
    发明专利
    Control equipments, control systems, and data generation methods 未知

    公开(公告)号：GB2512468A

    公开(公告)日：2014-10-01

    申请号：GB201402502

    申请日：2014-02-13

    Applicant: HITACHI LTD

    Inventor： SHIMAMURA KOTARO ,  SHIBATA NAOKI ,  KANEKAWA NOBUYASU ,  KURIHARA NAOKI

    IPC: H04L29/06 ,  G05B23/02

    Abstract: Control equipment has a plurality of processing modules 101, 102 performing the same processing and whose results are compared to detect a malfunction in the processing modules. Transmission of data is cut off at the time of detection of the malfunction. A check code concatenation circuit 131 concatenates the processing result outputted by one module 101 with a check code generated on the basis of the result of another module 102, and outputs the processing result concatenated with the check code.

    4.
    发明专利
    未知

    公开(公告)号：DE69431374T2

    公开(公告)日：2003-04-30

    申请号：DE69431374

    申请日：1994-10-12

    Applicant: HITACHI LTD

    Inventor： KANEKAWA NOBUYASU ,  SHOJI SUZUKI ,  SATO YOSHIMICHI ,  TASHIRO KOREFUMI ,  KEISUKE BEKKI ,  SATO HIROSHI ,  NOHMI MAKOTO ,  OHTSUJI SHINYA

    IPC: G05B9/03 ,  G05B13/02 ,  G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/267 ,  G06F17/50 ,  H03K19/007

    Abstract: The present invention relates to a self-checking circuit and a method of its configuration. More particularly, it concerns a self-checking circuit useful for highly reliable system configuration. As for a logic circuit having error detection function that has function blocks of feeding out a plurality of signals at least duplexed, compares the output signals of the function blocks, and detects an error on the basis of results of the comparison, it comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect the error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to the both output signals exist.

    ELECTRONIC CIRCUIT PACKAGE
    6.
    发明专利
    ELECTRONIC CIRCUIT PACKAGE 未知

    公开(公告)号：CA2205528A1

    公开(公告)日：1992-08-29

    申请号：CA2205528

    申请日：1992-02-27

    Applicant: HITACHI LTD

    Inventor： OKISHIMA TETSUYA ,  IHARA HIROKAZU ,  AKIYAMA MASATSUGU ,  YAMANAKA HISAYOSHI ,  KANEKAWA NOBUYASU ,  KAWABATA KIYOSHI

    IPC: H05K1/16

    Abstract: A data processing apparatus includes a microprocessor which processes data and outputs m bits of data simultaneously and a semiconductor chip module. The module has a plurality of memory chips having data width of n bits data formed on each side of a substrate. The apparatus further includes data lines connected to the microprocessor and the memory chips for slicing m bit data into n bit data and providing the sliced n bit data to each memory chip. The data of a data processing apparatus is transmitted by the microprocessor and the memory chips. The microprocessor outputs an address signal to the memory chips. One group of the memory chips outputs data upper n bits to the microprocessor in parallel based on the address signal. The other group of the memory chips outputs data of lower (m-n) bits to the microprocessor in parallel based on the address signal.

    9.
    发明专利
    未知

    公开(公告)号：DE69534349D1

    公开(公告)日：2005-09-01

    申请号：DE69534349

    申请日：1995-12-20

    Applicant: HITACHI LTD

    Inventor： SATO HIROSHI ,  KANEKAWA NOBUYASU ,  NOHMI MAKOTO ,  TASHIRO KOREFUMI

    IPC: B60L3/08 ,  B61L3/00 ,  B61L3/22 ,  B61L15/00 ,  G05B9/02 ,  G05B9/03 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G08C25/00

    Abstract: The object of the present invention is to provide a controller and a system having a highly reliable fail safe function. An ATP device which generates control data for the two systems from an ATP command speed signal, duplicates the logic unit in the ATP device so as to process each control data, provides at least two CRC data for checking the control data for each system, and changes the CRC data of the opposite logic units or selects one of the two according to the content of a failure detection signal from each of the duplicated logic units. It is realized to check the control data and the operation of each logic circuit and only when all the data, circuits, and elements operate normally, an output signal for controlling the object to be controlled is outputted and when a failure is detected in a part, an output signal is outputted. Therefore, when a failure occurs, a fail safe function for controlling on the safety side is made possible.

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