中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

101 records (took 0.026 seconds)

    2.
    发明专利
    未知

    公开(公告)号：DE3428424A1

    公开(公告)日：1985-02-14

    申请号：DE3428424

    申请日：1984-08-01

    Applicant: HITACHI LTD

    Inventor： YAMAOKA HIROMASA ,  OKAMOTO TADASHI ,  IWASA YUZABURO ,  KIMURA KOUICHI

    IPC: G06F9/32 ,  G05B19/05 ,  G06F9/30 ,  G06F9/02 ,  G06F15/46 ,  G05B15/02 ,  G05B21/02

    Abstract: A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.

    4.
    发明专利
    未知

    公开(公告)号：DE3484319D1

    公开(公告)日：1991-05-02

    申请号：DE3484319

    申请日：1984-02-17

    Applicant: HITACHI LTD

    Inventor： OKAMOTO TADASHI ,  YAMAOKA HIROMASA

    IPC: G06F15/16 ,  G05B19/05 ,  G06F9/00 ,  G06F9/38 ,  G06F9/46 ,  G06F12/00 ,  G06F15/80 ,  G06F15/46

    Abstract: A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory (1) for simplifying the programming, while the operands are stored in memories (61, 62; 71,72) each incorporated in each of the processors (3, 4) adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors (3, 4) in parallel with one another. Overall processing speed is made thus significantly high.

    5.
    发明专利
    未知

    公开(公告)号：BR8403767A

    公开(公告)日：1985-07-02

    申请号：BR8403767

    申请日：1984-07-27

    Applicant: HITACHI LTD

    Inventor： YAMAOKA HIROMASA ,  OKAMOTO TADASHI ,  IWASA YUZABURO ,  KIMURA KOICHI

    IPC: G06F9/32 ,  G05B19/05 ,  G06F9/30 ,  G06F7/00

    Abstract: A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.

    6.
    发明专利
    未知

    公开(公告)号：BR8400810A

    公开(公告)日：1984-10-02

    申请号：BR8400810

    申请日：1984-02-22

    Applicant: HITACHI LTD

    Inventor： OKAMOTO TADASHI ,  YAMAOKA HIROMASA

    IPC: G06F15/16 ,  G05B19/05 ,  G06F9/00 ,  G06F9/38 ,  G06F9/46 ,  G06F12/00 ,  G06F15/80 ,  G06F15/20 ,  G05B19/18

    Abstract: A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory (1) for simplifying the programming, while the operands are stored in memories (61, 62; 71,72) each incorporated in each of the processors (3, 4) adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors (3, 4) in parallel with one another. Overall processing speed is made thus significantly high.

Patent Agency Ranking