公开(公告)号：WO1996005557A1

公开(公告)日：1996-02-22

申请号：PCT/US1995010231

申请日：1995-08-10

Applicant: HONEYWELL INC.

Inventor： HONEYWELL INC. ,  DRISCOLL, Kevin, R.

IPC: G06F11/18

CPC classification number: G06F11/1604 ,  G06F1/14 ,  G06F11/183

Abstract: This invention relates to fault-tolerant real-time clock capable of withstanding n-faults, including Byzantine faults. In particular, the instant invention produces redundant clock signals which have low skew with respect to each other, operate with extremely high accuracy, and can be constructed without use of analog electric components, with the exception of oscillators. The present fault tolerant clock is composed of three types of electrical subcircuits coupled together: oscillators/counters, sequential edge voters, and regular voters. Each of these cubcircuits can be duplicated and coupled appropriately as needed to form a clock mechanism tolerant of any number of faults in the clock circuitry while maintaining an extremely precise timing mechanism suitable for accurately integrating and differentiating signals with respect to time.

Abstract translation: 本发明涉及能承受包括拜占庭故障在内的n个故障的容错实时时钟。 特别地，本发明产生了相对于彼此具有低偏斜度的冗余时钟信号，以非常高的精度进行操作，并且除了振荡器之外，可以构造为不使用模拟电气部件。 目前的容错时钟由耦合在一起的三种类型的电气电路组成：振荡器/计数器，顺序边缘选择器和常规选择器。 这些立方电路中的每一个可以根据需要被适当地复制和耦合，以形成能够承受时钟电路中任何数量的故障的时钟机制，同时保持适合于相对于时间精确地积分和区分信号的非常精确的定时机制。

公开(公告)号：WO1994023510A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003504

申请日：1994-03-31

Applicant: HONEYWELL INC.

Inventor： HONEYWELL INC. ,  DRISCOLL, Kevin, R. ,  HOYME, Kenneth, P.

IPC: H04L01/06

CPC classification number: H04L1/22 ,  H04L1/06 ,  H04L1/08

Abstract: An apparatus and method for transmitting information between dual redundant components comprises two information sources, each of which is coupled to two transmitters, the outputs of which are coupled to four signal paths for transmission to two independent voters. Each of the voters compares predetermined pairs of the signals on the four signal paths and provides a preferred one of the signals to a corresponding receiver based on the results of the pair comparisons.

Abstract translation: 用于在双冗余部件之间传输信息的装置和方法包括两个信息源，每个信息源耦合到两个发射器，其两个发射器耦合到四个信号路径，以传输给两个独立的选择器。 每个投票者在四个信号路径上比较预定的信号对，并且基于对比较的结果向对应的接收机提供优选的一个信号。

公开(公告)号：WO1994015420A1

公开(公告)日：1994-07-07

申请号：PCT/US1993012204

申请日：1993-12-14

Applicant: HONEYWELL INC.

Inventor： HONEYWELL INC. ,  DRISCOLL, Kevin, R.

IPC: H04L01/22

CPC classification number: G06F11/08 ,  G06F11/1625 ,  H04L9/004 ,  H04L9/08

Abstract: A fault detection apparatus and method combines each of a plurality of redundant digital data signals with a unique key signal for transmission over one of a plurality of signal lines and recombines each with its unique key signal at a receiving end. The recombined signals are then compared at the receiving end to detect certain faults between or among the plurality of what should be identical received signals.

Abstract translation: 故障检测装置和方法将多个冗余数字数据信号中的每一个与唯一的键信号组合，用于在多条信号线中的一条信号线上传输，并在接收端重新组合其唯一的键信号。 然后在接收端比较重新组合的信号以检测多个应该是相同的接收信号之间或之间的某些故障。

公开(公告)号：WO1994023516A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003502

申请日：1994-03-31

Applicant: HONEYWELL INC.

Inventor： HONEYWELL INC. ,  DRISCOLL, Kevin, R.

IPC: H04L12/40

CPC classification number: H04L12/4015 ,  H04L12/4035 ,  H04L12/407

Abstract: A media access protocol provides a fixed frame length and limited arbitration among certain predetermined users by providing limited arbitration during certain fixed time slots of a table driven proportional access system.

Abstract translation: 媒体访问协议通过在表驱动比例访问系统的某些固定时隙期间提供有限仲裁来在某些预定用户之间提供固定的帧长度和有限的仲裁。

公开(公告)号：EP0775344A1

公开(公告)日：1997-05-28

申请号：EP95930152.0

申请日：1995-08-10

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R.

IPC: G06F1 ,  G06F11 ,  H03L7 ,  H04L7

CPC classification number: G06F11/1604 ,  G06F1/14 ,  G06F11/183

Abstract: This invention relates to fault-tolerant real-time clock capable of withstanding n-faults, including Byzantine faults. In particular, the instant invention produces redundant clock signals which have low skew with respect to each other, operate with extremely high accuracy, and can be constructed without use of analog electric components, with the exception of oscillators. The present fault tolerant clock is composed of three types of electrical subcircuits coupled together: oscillators/counters, sequential edge voters, and regular voters. Each of these cubcircuits can be duplicated and coupled appropriately as needed to form a clock mechanism tolerant of any number of faults in the clock circuitry while maintaining an extremely precise timing mechanism suitable for accurately integrating and differentiating signals with respect to time.

公开(公告)号：EP0676108B1

公开(公告)日：1996-11-13

申请号：EP94905395.3

申请日：1993-12-14

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R.

IPC: H04L1/22 ,  H04L1/24 ,  H04L9/00

CPC classification number: G06F11/08 ,  G06F11/1625 ,  H04L9/004 ,  H04L9/08

Abstract: A fault detection apparatus and method combines each of a plurality of redundant digital data signals with a unique key signal for transmission over one of a plurality of signal lines and recombines each with its unique key signal at a receiving end. The recombined signals are then compared at the receiving end to detect certain faults between or among the plurality of what should be identical received signals.

公开(公告)号：EP0692167A1

公开(公告)日：1996-01-17

申请号：EP94913993.0

申请日：1994-03-31

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R. ,  HOYME, Kenneth, P.

IPC: H04B1 ,  H04B3 ,  H04L1

CPC classification number: H04L1/22 ,  H04L1/06 ,  H04L1/08

Abstract: An apparatus and method for transmitting information between dual redundant components comprises two information sources, each of which is coupled to two transmitters, the outputs of which are coupled to four signal paths for transmission to two independent voters. Each of the voters compares predetermined pairs of the signals on the four signal paths and provides a preferred one of the signals to a corresponding receiver based on the results of the pair comparisons.

公开(公告)号：EP0692168A1

公开(公告)日：1996-01-17

申请号：EP94913992.0

申请日：1994-03-31

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R.

IPC: H04L29 ,  H04L12

CPC classification number: H04L12/4015 ,  H04L12/4035 ,  H04L12/407

Abstract: A media access protocol provides a fixed frame length and limited arbitration among certain predetermined users by providing limited arbitration during certain fixed time slots of a table driven proportional access system.

公开(公告)号：EP0676108A1

公开(公告)日：1995-10-11

申请号：EP94905395.0

申请日：1993-12-14

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R.

IPC: H04B3 ,  G06F11 ,  H04B17 ,  H04L9

CPC classification number: G06F11/08 ,  G06F11/1625 ,  H04L9/004 ,  H04L9/08

Abstract: A fault detection apparatus and method combines each of a plurality of redundant digital data signals with a unique key signal for transmission over one of a plurality of signal lines and recombines each with its unique key signal at a receiving end. The recombined signals are then compared at the receiving end to detect certain faults between or among the plurality of what should be identical received signals.

公开(公告)号：EP1142135B1

公开(公告)日：2004-10-20

申请号：EP99967538.2

申请日：1999-12-21

Applicant: HONEYWELL INC.

Inventor： DRISCOLL, Kevin, R.

IPC: H04B1/00

CPC classification number: H04L12/1854 ,  H04L12/1863 ,  H04L12/4035

Abstract: A communication protocol and hardware is provided which allows a meshed network to reliably perform in a real-time environment. The protocol establishes that a single node will transmit on the mesh at any given time. The transmitted message is propagated to all other nodes on the mesh by flooding the network. Immediately upon receiving each bit of data, a receiving node will immediately retransmit that bit, thereby increasing the speed of the flooding. Arbitration and lockout logic is provided which assures that nodes receiving data from multiple sources will be able to correctly handle and retransmit that data.