公开(公告)号：WO1989000279A2

公开(公告)日：1989-01-12

申请号：PCT/US1988002159

申请日：1988-06-22

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  BURNS, Richard, J. ,  GRIM, Kenneth, R. ,  LEVY, Miguel, E.

IPC: G01J01/00

CPC classification number: G01S13/288 ,  G06J1/005

Abstract: An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the associated sample and hold circuit (16) to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).

公开(公告)号：EP0322454B1

公开(公告)日：1991-02-27

申请号：EP88907499.3

申请日：1988-06-22

Applicant: Hughes Aircraft Company

Inventor： BURNS, Richard, J. ,  GRIM, Kenneth, R. ,  LEVY, Miguel, E.

IPC: G06J1/00 ,  G01S13/28

CPC classification number: G01S13/288 ,  G06J1/005

Abstract: An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the associated sample and hold circuit (16) to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).

公开(公告)号：EP0322454A1

公开(公告)日：1989-07-05

申请号：EP88907499.0

申请日：1988-06-22

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： BURNS, Richard, J. ,  GRIM, Kenneth, R. ,  LEVY, Miguel, E.

IPC: G01J1 ,  G01S7 ,  G01S13 ,  G06J1

CPC classification number: G01S13/288 ,  G06J1/005

Abstract: An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-­ 1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the asso­ ciated sample and hold cir­ cuit (16) to either be invert­ ed or noninverted when it is summed with other similar­ ly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively dis­ able certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits correspond­ ing to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).