公开(公告)号：WO1988002185A1

公开(公告)日：1988-03-24

申请号：PCT/US1987001707

申请日：1987-07-20

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  HENDERSON, Richard, C.

IPC: H01L27/02

CPC classification number: H01L27/12 ,  H01L27/11807

Abstract: An integrated circuit masterslice (2) in which a plurality of mutually spaced epitaxial columns (4) are formed on an insulative substrate (6). Each column (4) has successive pairs of n-channel FETs (10) alternating with successive pairs of p-channel FETs (8), the contacts of which are accessible by a surface metallization. Drain and source contacts (12, 16, 20, 24) are shared by adjacent FETs, and corresponding elements on adjacent columns are arranged in rows. The masterslice (2) accommodates a wide variety of circuits with a high density transistor grid and interconnect metallization.

Abstract translation: 一种其中多个相互间隔的外延柱（4）形成在绝缘衬底（6）上的集成电路主体（2）。 每列（4）具有与连续的p沟道FET（8）对交替的n沟道FET（10）的连续对，其触点可通过表面金属化访问。 漏极和源极触点（12,16,20,24）由相邻的FET共享，并且相邻列上的相应元件排列成行。 主板（2）可容纳各种具有高密度晶体管栅极和互连金属化的电路。

公开(公告)号：WO1988003703A1

公开(公告)日：1988-05-19

申请号：PCT/US1987002611

申请日：1987-10-13

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  HENDERSON, Richard, C. ,  GARVIN, Hugh, L. ,  BEAUBIEN, Randall, S. ,  RENSCH, David, B.

IPC: H01L21/00

CPC classification number: H01L21/0274 ,  G03F7/094 ,  H01L21/0277 ,  H01L21/31138 ,  H01L21/312

Abstract: A resist structure used in fabricating microelectronic devices on a substrate by lithography includes three layers, a thick planarizing layer (20) of a polymer material in contact with the substrate (12) and having a generally planar upper surface, a separating layer (26) overlying the planarizing layer (20), and an imaging layer (28) of a resist material overlying the separating layer (26). The separating layer (26) is a light transparent and electrically conductive material, preferably a mixture of indium oxide and tin oxide. An etched resist structure is formed on the substrate (12) by defining and developing a pattern in the imaging layer (28), transferring the pattern to the separating layer (26), and transferring the pattern to the planarizing layer (20).

Abstract translation: 用于通过光刻在衬底上制造微电子器件的抗蚀剂结构包括三层：与衬底（12）接触并具有大致平坦的上表面的聚合物材料的厚平坦化层（20），分离层（26） 覆盖所述平坦化层（20）和覆盖所述分离层（26）的抗蚀剂材料的成像层（28）。 分离层（26）是透光导电材料，优选氧化铟和氧化锡的混合物。 通过在成像层（28）中限定和显影图案，在基板（12）上形成蚀刻的抗蚀剂结构，将图案转移到分离层（26），并将图案转移到平坦化层（20）。

公开(公告)号：WO1985001613A1

公开(公告)日：1985-04-11

申请号：PCT/US1983001959

申请日：1983-12-12

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  CHEN, John, Y. ,  HENDERSON, Richard, C.

IPC: H01L21/76

CPC classification number: H01L21/762 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/8236

Abstract: A high-density MOSFET (10) having field oxide (24) self-aligned channel stops (26, 27) for device isolation and an optimal method of fabricating such a device. The process provides channel stops (26, 27) underlying and aligned with the edges of a field oxide layer (24) and allows the dopant concentration of the channel stops (26, 27) to be established separately from that of the active device channel region (16) by use of an independent channel stop implant. The active devices (10) thus formed require minimal isolation area, have a high field threshold voltage, a low junction capacitance, and minimal body effect. They are particularly useful in high-speed, high-performance integrated circuits.

Abstract translation: 具有用于器件隔离的场氧化物（24）自对准通道停止器（26,27）的高密度MOSFET（10）以及制造这种器件的最佳方法。 该过程提供在场氧化物层（24）的边缘下方并与其对准的通道停止（26,27），并且允许与有源器件沟道区域（26,27）的掺杂剂浓度分开设置， （16）通过使用独立的通道停止植入物。 由此形成的有源器件（10）需要最小的隔离面积，具有高场阈值电压，低结电容和最小的身体效应。 它们在高速，高性能集成电路中特别有用。

公开(公告)号：EP0281590B1

公开(公告)日：1992-07-08

申请号：EP87905678.6

申请日：1987-07-20

Applicant: Hughes Aircraft Company

Inventor： HENDERSON, Richard, C.

IPC: H01L27/02

CPC classification number: H01L27/12 ,  H01L27/11807

Abstract: An integrated circuit masterslice (2) in which a plurality of mutually spaced epitaxial columns (4) are formed on an insulative substrate (6). Each column (4) has successive pairs of n-channel FETs (10) alternating with successive pairs of p-channel FETs (8), the contacts of which are accessible by a surface metallization. Drain and source contacts (12, 16, 20, 24) are shared by adjacent FETs, and corresponding elements on adjacent columns are arranged in rows. The masterslice (2) accommodates a wide variety of circuits with a high density transistor grid and interconnect metallization.

公开(公告)号：EP0281590A1

公开(公告)日：1988-09-14

申请号：EP87905678.0

申请日：1987-07-20

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HENDERSON, Richard, C.

IPC: H01L21 ,  H01L27

CPC classification number: H01L27/12 ,  H01L27/11807

Abstract: Dans la tranche standardisée (2) à circuits intégrés, une pluralité de colonnes épitaxiales mutuellement espacées (4) sont formées sur un substrat isolant (6). Chaque colonne (4) possède des paires successives de transistors à effet de champ TECs à canaux n (10) s'alternant avec des paires successives de TECs à canaux p (8), dont les contacts sont accessibles par une métallisation de surface. Des contacts de drain et de source (12, 16, 20, 24) sont partagés par les TECs adjacents, et des éléments correspondant sur des colonnes adjacentes sont disposés en rangées. La tranche standardisée (2) accepte une grande variété de circuits avec une métallisation d'interconnexion et de grille de transistor de grande densité.

公开(公告)号：EP0289595A1

公开(公告)日：1988-11-09

申请号：EP88900613.0

申请日：1987-10-13

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HENDERSON, Richard, C. ,  GARVIN, Hugh, L. ,  BEAUBIEN, Randall, S. ,  RENSCH, David, B.

IPC: G03F7 ,  H01L21

CPC classification number: H01L21/0274 ,  G03F7/094 ,  H01L21/0277 ,  H01L21/31138 ,  H01L21/312

Abstract: A resist structure used in fabricating microelectronic devices on a substrate by lithography includes three layers, a thick planarizing layer (20) of a polymer material in contact with the substrate (12) and having a generally planar upper surface, a separating layer (26) overlying the planarizing layer (20), and an imaging layer (28) of a resist material overlying the separating layer (26). The separating layer (26) is a light transparent and electrically conductive material, preferably a mixture of indium oxide and tin oxide. An etched resist structure is formed on the substrate (12) by defining and developing a pattern in the imaging layer (28), transferring the pattern to the separating layer (26), and transferring the pattern to the planarizing layer (20).

Abstract translation: 通过光刻在衬底上制造多电子器件中使用的抗蚀剂结构包括三层，与衬底（12）接触并具有大致平坦的上表面的聚合物材料的平坦厚层（20），层 覆盖平坦层（20）的分离构件（26）和覆盖分离层（26）的抗蚀剂材料的成像层（28）。 分离层（26）由透光且导电的材料制成，优选氧化铟和氧化锡的混合物。 通过在成像层（28）中限定并显影图案，将图案转印到释放层（26）上，并将图案转印到基底（12）上，从而形成蚀刻的抗蚀剂结构 平面性（20）。

公开(公告)号：EP0157780B1

公开(公告)日：1988-05-18

申请号：EP84900564.0

申请日：1983-12-12

Applicant: Hughes Aircraft Company

Inventor： CHEN, John, Y. ,  HENDERSON, Richard, C.

IPC: H01L21/76

CPC classification number: H01L21/762 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/8236

Abstract: A high-density MOSFET (10) having field oxide (24) self-aligned channel stops (26, 27) for device isolation and an optimal method of fabricating such a device. The process provides channel stops (26, 27) underlying and aligned with the edges of a field oxide layer (24) and allows the dopant concentration of the channel stops (26, 27) to be established separately from that of the active device channel region (16) by use of an independent channel stop implant. The active devices (10) thus formed require minimal isolation area, have a high field threshold voltage, a low junction capacitance, and minimal body effect. They are particularly useful in high-speed, high-performance integrated circuits.

公开(公告)号：EP0157780A1

公开(公告)日：1985-10-16

申请号：EP84900564.0

申请日：1983-12-12

Applicant: Hughes Aircraft Company

Inventor： CHEN, John, Y. ,  HENDERSON, Richard, C.

IPC: H01L21 ,  H01L29

CPC classification number: H01L21/762 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/8236

Abstract: MOSFET à densité élevée (10) possédant des arrêts de canaux auto-alignés (26, 27) d'oxyde de champ (24) pour l'isolation du dispositif et procédé optimal de fabrication d'un tel dispositif. Le procédé permet de réaliser des arrêts de canaux (26, 27) sous-jacents et alignés avec les bords d'une couche d'oxyde de champ (24) et permet à la concentration de dopant des arrêts de canaux (26, 27) d'être fixée séparément de celle de la région de canaux du dispositif actif (16) en utilisant un implant d'arrêt de canal indépendant. Les dispositifs actifs (10) ainsi formés ne requièrent qu'une zone minimale d'isolation, présentent une tension élevée de seuil de champ, une faible capacitance de jonction et un effet de corps minime. Ils sont particulièrement utiles dans des circuits intégrés à haute vitesse et performances élevées.