公开(公告)号：WO1989002201A2

公开(公告)日：1989-03-09

申请号：PCT/US1988002865

申请日：1988-08-19

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  STONE, Wade, J. ,  KELLEY, Edwin, A.

IPC: H04L25/02

CPC classification number: H04L25/02

Abstract: According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

公开(公告)号：WO1989002120A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002850

申请日：1988-08-18

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  KELLEY, Edwin, A. ,  BALLER, Howard, H. ,  CONILOGUE, Randall, L.

IPC: G06F07/50

CPC classification number: G06F7/509

Abstract: A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.

公开(公告)号：EP0344226B1

公开(公告)日：1993-05-05

申请号：EP88907975.2

申请日：1988-08-18

Applicant: Hughes Aircraft Company

Inventor： KELLEY, Edwin, A. ,  BALLER, Howard, H. ,  CONILOGUE, Randall, L.

IPC: G06F7/50

CPC classification number: G06F7/509

Abstract: A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.

公开(公告)号：EP0344226A1

公开(公告)日：1989-12-06

申请号：EP88907975.0

申请日：1988-08-18

Applicant: Hughes Aircraft Company

Inventor： KELLEY, Edwin, A. ,  BALLER, Howard, H. ,  CONILOGUE, Randall, L.

IPC: G06F7

CPC classification number: G06F7/509

Abstract: A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connect­ ed to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipa­ tion at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are conti­ guous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.

公开(公告)号：EP0335946B1

公开(公告)日：1993-12-01

申请号：EP88909156.7

申请日：1988-08-19

Applicant: Hughes Aircraft Company

Inventor： STONE, Wade, J. ,  KELLEY, Edwin, A.

IPC: H04L25/02

CPC classification number: H04L25/02

Abstract: According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

公开(公告)号：EP0335946A1

公开(公告)日：1989-10-11

申请号：EP88909156.0

申请日：1988-08-19

Applicant: Hughes Aircraft Company

Inventor： STONE, Wade, J. ,  KELLEY, Edwin, A.

IPC: H03K17 ,  H03K19 ,  H04L25

CPC classification number: H04L25/02

Abstract: Selon l'invention, un système de communication de données numériques à haute vitesse utilise un réseau de circuit en mode courant en tant que dispositifs d'entrée et de sortie aux extrémités d'une ligne de transmission telles que les interconnexions entre des puces de circuit intégré. D'une manière spécifique un commutateur d'attaque en mode courant génère des amplitudes de courant de sortie sensibles à une source d'un signal numérique représentatif de données à transmettre. La sortie du commutateur est connectée à l'entrée d'une ligne de transmission. La sortie de la ligne de transmission est connectée à l'entrée d'un circuit récepteur qui répond aux amplitudes de courant et possède une entrée à un niveau de tension à peu près constant. Le circuit de réception est un transistor connecté dans une configuration de base commune. L'émetteur du transistor est connecté à la sortie de la ligne de transmission. La base du transistor est connectée à une source de tension constante. Un dispositif de formation d'impulsion sous la forme d'une bascule électronique de Schmitt possède une réaction positive de la sortie vers l'entrée. Le réseau de circuit en mode courant décrit est incorporé dans une puce de circuit intégré.