Abstract:
A chip carrier array (10) which includes interconnected chip carriers (11) separated from each other and from the substrate waste edge (25) by elongated slots (15) which define outer edges of the chip carriers (11). More particularly, each chip carrier (11) includes corners which are defined by elongated slots (15). Each chip carrier (11) includes a plurality of electrically isolated edge interconnects (19) which wrap around edges defined by the elongated slots (15).
Abstract:
A process for forming electrically conductive circuitry on a metallic nonconductive substrate or insulating layer which includes the steps of providing a nonconductive ceramic substrate having a metallic component and which can dissociate into its constituent components to provide dissociated metal bonded to the ceramic substrate upon application of laser energy. Laser energy is then applied to predetermined areas of the surface of the nonconductive ceramic substrate to provide dissociated metallic conductors in the predetermined areas. The disclosed process further includes the formation of metallized through holes by application of laser energy to the nonconductive ceramic substrate to form a through hole, whereby dissociated metal is formed on the inside of the through hole. The disclosed process also includes the capability to down trim a thick film or thin film resistor which is conductively coupled between two areas of metallization. Laser energy is applied to a portion of the thick film or thin film resistor and to a portion of the metallic nonconductive ceramic substrate in a predetermined pattern to provide a continuous dissociated metallic conductor which passes through the thick film or thin film resistor and is conductively connected to one of two areas of electrically conductive metallization.
Abstract:
A chip carrier array (10) which includes interconnected chip carriers (11) separated from each other and from the substrate waste edge (25) by elongated slots (15) which define outer edges of the chip carriers (11). More particularly, each chip carrier (11) includes corners which are defined by elongated slots (15). Each chip carrier (11) includes a plurality of electrically isolated edge interconnects (19) which wrap around edges defined by the elongated slots (15).
Abstract:
Matrice (10) avec supports de puces comprenant des supports (12) de puces entre eux et séparés les uns des autres et par rapport au bord ineffectif (25) du substrat par des fentes allongées (15) qui définissent les bords extérieurs des supports (11) de puces. Et plus particulièrement, chaque support (11) de puces comprend des coins qui sont définis par des fentes allongées (15). Chaque support (11) de puces comprend une pluralité d'interconnexions (19) de bords électriquement isolés qui enveloppent les bords définis par les fentes allongées (15).