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公开(公告)号:JP2001312514A
公开(公告)日:2001-11-09
申请号:JP2001076506
申请日:2001-03-16
Applicant: HYNIX SEMICONDUCTOR INC , KOREA ELECTRONICS TELECOMM
Inventor: CHIN TOKEI , KIM HAE KWANG , KIN BUNTETSU , KIN SHINYU
Abstract: PROBLEM TO BE SOLVED: To express a large number of attribute values with bits constituting vector descriptors for multi-medial data and rearrange them, and then, to hierarchically express and store the vector descriptors corresponding to the number of the attribute values and to retrieve the multi-media data using the stored representation data. SOLUTION: In the multi-media data retrieval system and method large number of the attribute values described by vector descriptor are quantized and the quantized attribute values are expressed in a bit format, the attribute values expressed in the bit format are rearranged in the order from the highest position bit to the lowest position bit, and the vector descriptors are hierarchically expressed. The number of the rearranged attribute values and the attribute values being entered are encoded as variable length codes, and stored only the variable length attribute value among the stored attributes corresponding to the number of the attribute values are reversely encoded in variable length to be rearranged reversely and the original attribute values are restored. The restored attribute values are reversely quantized and the reversed quantized attribute values are compared with the attribute value already stored in a multi-media database, and the multi-media data are searched.
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公开(公告)号:JP2004311932A
公开(公告)日:2004-11-04
申请号:JP2003388267
申请日:2003-11-18
Applicant: Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
Inventor: KIN TOSHAKU , LEE HO-SEOK , PARK BYUNG-JUN , KWON IL-YOUNG , RI SHOMIN , KIN KEISHU , KIN SHINYU , CHOI HYUNG-BOK , SHIN DONG-WOO
IPC: H01L21/8242 , G11C8/02 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/108
CPC classification number: H01L27/10855 , H01L27/0207 , H01L27/10814
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element and a manufacturing method for the same, which prevent short circuit between the lower electrodes of a capacitor caused by the leaning and/or lifting of the electrodes upon forming the electrodes and increase an effective capacitor area to secure sufficient charge storage volume. SOLUTION: The semiconductor element comprises a plurality of plugs (61), which are arranged at every identical distance and whose centers are at the intersections (01, 02) between X-axis virtual lines (X1, X2) and Y-axis virtual lines (Y1, Y2), respectively, and a plurality of capacitor lower electrodes (62), which are arranged at every identical distance and each of which corresponds and connects electrically to each plug (61). The lower electrodes (62) are of octagonal or circular shapes. The centers of a pair of the lower electrodes (62A, 62B) adjacent to each other in the direction of the Y-axis virtual line (Y1) are set at the points (01", 01') that give different X coordinates on the X-axis virtual lines (X1, X2), respectively, so that the area of each part of the electrodes (62A, 62B) that opposite in the direction of the Y-axis virtual line (Y1) is minimum. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题:提供一种半导体元件及其制造方法,其防止在形成电极时由电极的倾斜和/或提升引起的电容器的下部电极之间的短路,并且增加 有效的电容器面积,以确保充足的电量存储量。 解决方案:半导体元件包括多个插头(61),它们以相同的距离布置,其中心位于X轴假想线(X1,X2)和Y轴之间的交点(01,02) (Y1,Y2)和多个电容器下电极(62),它们以相同的距离布置,并且每个相应的距离对应并与每个插头(61)电连接。 下部电极(62)为八边形或圆形。 在Y轴虚线(Y1)的方向上彼此相邻的一对下电极(62A,62B)的中心被设定在在其上给出不同X坐标的点(01“,01')上 X轴虚拟线(X1,X2),使得与Y轴虚拟线(Y1)的方向相反的电极(62A,62B)的各部分的面积最小。 (C)2005,JPO&NCIPI
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公开(公告)号:JP2001230320A
公开(公告)日:2001-08-24
申请号:JP2000391991
申请日:2000-12-25
Applicant: HYNIX SEMICONDUCTOR INC
Inventor: KIN SHINYU
IPC: H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a self-aligned contact utilizing selective epitaxial growth. SOLUTION: The method for forming a self-aligned contact comprises a step for forming work lines and contract regions exposed between the word lines on a semiconductor substrate, a step for forming a contact plug epitaxial layer on the contact regions, a step for forming an air gap above a noncontact region where the epitaxial layer is not formed by depositing an interlayer insulation film on the entire structure, and a step for exposing the upper part of the epitaxial layer by patterning the interlayer insulation film.
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