公开(公告)号：WO1995005633A2

公开(公告)日：1995-02-23

申请号：PCT/US1994008601

申请日：1994-08-01

Applicant: HYUNDAI ELECTRONICS AMERICA, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  RARICK, Leonard, Dennis

IPC: G06F07/50

CPC classification number: G06F7/5318 ,  G06F7/49947 ,  G06F7/508

Abstract: A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage then uses the generate and propagate data to generate at least one final carry. Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.

Abstract translation: 用于添加加数和加法并产生最终和的进位前瞻加法器。 加法，加法和最后的和是二进制数，每个都有多个位。 加数和加法中相同顺序的位被组织成列。 加法器具有至少一个数据缩减级，每个数据缩减级具有至少一个多列全加器。 数据缩减阶段使用加数和加数位列来生成减少的加数和减小的加法，减少的加法比具有比加法器少的位。 生成/传播计算阶段然后使用减少的加数和减小的加法来计算生成和传播数据，生成/传播计算阶段已被修改以减少加数和加减。 进位生成阶段然后使用生成和传播数据来生成至少一个最终进位。 最后，最终计算阶段使用减少的加数，减少的加法，以及计算最终总和的最终计算阶段。 数据减少级将输入减少到生成/传播计算级，从而减少进位产生电路的输入数。 通过较少的输入，可以减少进位产生电路中的级数，从而导致进位前进加法器的更快实现。

公开(公告)号：WO1996017295A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015043

申请日：1995-11-20

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC. ,  ISAMAN, David, L.

IPC: G06F09/40

CPC classification number: G06F9/3844

Abstract: A branch prediction technique which increases the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that many branches have run lengths that are constant or slowly-varying, i.e. several consecutive runs of 1's are of the same length. The technique uses the history stored for each branch, which history is enhanced by two small counters (102, 113), an up counter (102) and a down counter (113). These counters (102, 113) operate in conjunction with a state machine branch predictor (101) of the prior art for very accurate predictions.

Abstract translation: 提出了一种提高正确预测条件转移指令方向的可能性的分支预测技术。 该技术基于观察，许多分支的运行长度是恒定的或缓慢变化的，即1的连续运行的长度是相同的。 该技术使用为每个分支存储的历史，该历史由两个小计数器（102,113），向上计数器（102）和向下计数器（113）增强。 这些计数器（102,113）与现有技术的状态机分支预测器（101）一起工作，用于非常准确的预测。

公开(公告)号：WO1995004964A1

公开(公告)日：1995-02-16

申请号：PCT/US1994008714

申请日：1994-08-01

Applicant: HYUNDAI ELECTRONICS AMERICA, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  RARICK, Leonard, Dennis

IPC: G06F07/38

CPC classification number: G06F7/5318 ,  G06F7/509

Abstract: A carry-save adder for use in a binary multiplier with a reduced number of full adder stages. The carry-save adder is summing columns of binary data and is implemented with a plurality of one-bit (30) and two-bit (60) full adders. The one-bit (30) and two-bit (60) full adders are configured in a plurality of interconnected modified Wallace-Tree adders, each Wallace-Tree adder for summing binary data bits from one or more columns and generating a partial sum (74) and a partial carry (76). Each modified Wallace-Tree adder has a plurality of stages (70, 110, 130, 150) comprising one-bit (30) and two-bit (60) full adders for reducing the number of the binary data bits, the last stage (36, 122, 142, 162) comprising a single one-bit full adder (36, 122, 142, 162) for generating the partial sum (74) and the partial carry results (76). A plurality of conductors interconnects the stages of each modified Wallace-Tree adder with stages in the same Wallace-Tree adder and with stages in other modified Wallace-Tree adders.

Abstract translation: 一种进位保存加法器，用于具有减少数量的全加器级的二进制乘法器。 进位保存加法器是二进制数据的加法列，并且用多个一位（30）和两位（60）全加器实现。 一个位（30）和两位（60）全加法器配置在多个互连的修改的Wallace-Tree加法器中，每个Wallace-Tree加法器用于从一个或多个列求和二进制数据位，并产生部分和（ 74）和部分进位（76）。 每个修改的华莱士树加法器具有多个级（70,110,130,150），其包括用于减少二进制数据位的数量的一位（30）和两位（60）全加器，最后一级 包括用于产生部分和（74）和部分进位结果（76）的单个一位全加器（36,122,142,162）。 多个导体将每个修改的Wallace-Tree加法器的阶段与相同的Wallace-Tree加法器中的阶段和其他修改的Wallace-Tree加法器中的阶段相互连接。

公开(公告)号：WO1997037490A1

公开(公告)日：1997-10-09

申请号：PCT/US1997005228

申请日：1997-03-31

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  BEDARD, Karen

Inventor： HYUNDAI ELECTRONICS AMERICA, INC.

IPC: H04N05/445

CPC classification number: H04N21/42204 ,  H04N5/44543 ,  H04N5/50 ,  H04N5/782 ,  H04N21/4316 ,  H04N21/4334 ,  H04N21/4345 ,  H04N21/458 ,  H04N21/47 ,  H04N21/4755 ,  H04N21/482 ,  H04N21/8133

Abstract: A method and apparatus coupled to broadcast signals, such as television signals, and a television set (16) for displaying broadcast programs and channels. The apparatus displays broadcast programs on selected channels to a viewer, marks one or more of the programs in response to a first signal from the viewer, marks one or more of the channels in response to a second signal from the viewer, stores signals corresponding to the marked programs and channels; and sequentially displays the marked programs and channels in response to a third signal from the viewer. The apparatus displays a plurality of icons (51-58) on the screen, sequentially moves an icon cursor (42) from one icon to another icon in response to a first signal from a television viewer to point to one icon at a time, and displays text associated with the pointed icon only.

Abstract translation: 耦合到诸如电视信号的广播信号的方法和装置以及用于显示广播节目和频道的电视机（16）。 该装置将所选频道上的广播节目显示给观看者，响应于来自观众的第一信号标记一个或多个节目，响应于来自观众的第二信号标记一个或多个频道，存储对应于 标记的节目和频道; 并且响应于来自观众的第三信号顺序地显示标记的节目和频道。 该装置在屏幕上显示多个图标（51-58），响应于来自电视观看者的第一信号，一次将图标光标（42）从一个图标移动到另一个图标，以一次指向一个图标，以及 仅显示与指向图标相关联的文本。

公开(公告)号：WO1997018670A1

公开(公告)日：1997-05-22

申请号：PCT/US1996018114

申请日：1996-11-12

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  BEDARD, Karen

Inventor： HYUNDAI ELECTRONICS AMERICA, INC.

IPC: H04N05/50

CPC classification number: H04N21/47214 ,  H04N5/44543 ,  H04N21/42204 ,  H04N21/4316 ,  H04N21/47 ,  H04N21/482

Abstract: An intuitively operated Electronic Program Guide (EPG) which presents program guide information in table form at two levels of resolution. Schedule information is presented in icon form (500) over a long time window while textual information (510) is presented for a viewer-selected time slot. The selected time slot may appear to be a magnified representation (512) of the long time window view. In this way, a television screen of conventional resolution may present at least five hours of schedule information for eight channels. The viewer may operate the Electronic Program Guide (EPG) intuitively with simple remote control commands.

Abstract translation: 一个直观操作的电子节目指南（EPG），以两种分辨率的表格形式呈现节目指南信息。 在长时间窗口中以图标形式（500）呈现计划信息，同时为观看者选择的时隙呈现文本信息（510）。 所选择的时隙可以看起来是长时间窗口视图的放大表示（512）。 以这种方式，常规分辨率的电视屏幕可以呈现至少五个小时的八个频道的时间表信息。 观看者可以通过简单的遥控命令直观地操作电子节目指南（EPG）。

公开(公告)号：WO1996037983A1

公开(公告)日：1996-11-28

申请号：PCT/US1996007105

申请日：1996-05-16

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  RAO, R., Padmanabha ,  SICCARDO, Paolo, L. ,  LEVESQUE, Gilbert

Inventor： HYUNDAI ELECTRONICS AMERICA, INC.

IPC: H04L05/16

CPC classification number: H04N7/17336 ,  H04H20/38 ,  H04H20/81 ,  H04H60/94 ,  H04L12/2801 ,  H04L12/2856 ,  H04L12/2883 ,  H04L12/4633 ,  H04L47/2408 ,  H04M11/062 ,  H04N7/108 ,  H04N7/148 ,  H04N7/173 ,  H04N7/17354 ,  H04N21/222 ,  H04N21/2362 ,  H04N21/2365 ,  H04N21/4347 ,  H04N21/47202 ,  H04N21/47208 ,  H04N21/6125 ,  H04N21/6137 ,  H04N21/6377 ,  H04N21/64307 ,  H04N21/64784 ,  H04N21/658 ,  H04N21/6581 ,  H04N21/6587

Abstract: An architecture (200) for distributing digital information to subscriber units (202) wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface (206). The intermediate interface (206) selects the desired service from a broadband network and transmits it to the subscriber unit (202) over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit (202) may access a wide variety of digital information available on the broadband network. Universal broadband access is thus provided at low cost. Output bandwidth of broadcast equipment may also be optimized.

Abstract translation: 一种用于向用户单元（202）分发数字信息的架构（200），其中通过从用户单元向中间接口（206）发送调谐命令来实现多个数字服务之间的选择。 中间接口（206）从宽带网络中选择所需的服务，并通过带宽限制的接入线路将其发送到用户单元（202）。 带宽有限的接入线路可以用现有的基础设施来实现，而用户单元（202）可以访问宽带网络上可用的各种数字信息。 因此以低成本提供通用宽带接入。 广播设备的输出带宽也可以优化。

公开(公告)号：WO1996034335A1

公开(公告)日：1996-10-31

申请号：PCT/US1996004504

申请日：1996-04-02

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC. ,  ISAMAN, David, L.

IPC: G06F09/30

CPC classification number: G06F9/30094 ,  G06F9/30101 ,  G06F9/327 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861

Abstract: Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache (210) or from main memory, an instruction FIFO memory (220) for storing fetched instructions from the fetch stage, and an instruction decode stage (230) for removing instructions from the FIFO memory (220) in accordance with relative ages of instructions stored in the FIFO memory (220). The decode stage examines instructions removed from the FIFO memory (220) for trapping conditions, and flushes all younger instructions from the FIFO memory (220) in response to identification of a trap in an instruction. The decode stage (230) distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage (230) immediately causes the fetch address to be changed to the appropriate trap handler address.

Abstract translation: 用于检测和执行在多个流水线指令上操作的超标量处理器中的捕获程序指令的装置包括：用于从指令高速缓存（210）或从主存储器取出连续指令的提取级，用于存储读取的指令的指令FIFO存储器（220） 以及用于根据存储在FIFO存储器（220）中的指令的相对年龄从FIFO存储器（220）去除指令的指令解码级（230）。 解码阶段检查从FIFO存储器（220）中移除的用于捕获条件的指令，并且响应于指令中的陷阱的识别，刷新来自FIFO存储器（220）的所有较年轻的指令。 解码级（230）区分硬件陷阱和软件陷阱。 软件陷阱指令被转发到执行阶段执行。 解码级（230）立即使获取地址更改为适当的陷阱处理程序地址。

公开(公告)号：WO1996021278A1

公开(公告)日：1996-07-11

申请号：PCT/US1995017051

申请日：1995-12-29

Applicant: HYUNDAI ELECTRONICS AMERICA, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  OH, Jong-Hoon

IPC: H03K21/00

CPC classification number: G11C7/1018 ,  H03K23/004

Abstract: A counter system has a first counter (1) seeded by several input signals and a second counter (2) seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence or a sequential count sequence.

Abstract translation: 计数器系统具有由几个输入信号接合的第一计数器（1）和由第一计数器的至少第一输出种子的第二计数器（2）。 选择信号被输入到第二计数器以选择使用交错计数序列或顺序计数序列。