公开(公告)号：EP1586986A3

公开(公告)日：2008-10-29

申请号：EP04030004.8

申请日：2004-12-17

Applicant: Hitachi, Ltd.

Inventor： Fujimoto, Kazuhisa ,  Hosoya, Mutsumi ,  Watanabe, Naoki ,  Shimada, Kentaro

IPC: G06F3/06

CPC classification number: G06F12/0866 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0661 ,  G06F3/067 ,  G06F12/0813

Abstract: To provide a storage system with a cost/ performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units (10) and data caching control units (21) are connected to each other through an interconnection (31), the data caching control units (21) are divided into plural control clusters (70), each of the control clusters including at least two or more data caching control units (21), control of a cache memory (111) is conducted independently for each of the control clusters (70), and one of the plural data caching control units (21) manages, as a single system; protocol transformation units (10) and the plural control clusters (70) based on management information stored in a system management information memory unit (160).

公开(公告)号：EP2192480A1

公开(公告)日：2010-06-02

申请号：EP09251221.9

申请日：2009-04-29

Applicant: Hitachi Ltd.

Inventor： Mannen, Akihiro ,  Shimada, Kentaro

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0866

Abstract: In a storage control apparatus provided therein with a battery-backed-up memory device being a combination of a cache memory of a storage device and a system memory on the side of a CPU, an ASIC (Application-Specific Integrated Circuit) having a virtual window function is provided to a system, and I/O from a front end and/or a back end is performed via a virtual window, thereby making an addition of data integrity code, and performing automatic dual write of data. With such a storage control apparatus provided therein with a battery-backed-up memory being a combination of a CS/DS (Code Storage/Data Storage) and a cache, implemented are protection of block data, and dual write into a Cache (user data, control data) so that the reliability can be kept at the time of data input/output control.

Abstract translation: 在其中设置有作为存储装置的高速缓冲存储器和CPU侧的系统存储器的组合的电池备份存储装置的存储控制装置中，具有虚拟存储器的ASIC（专用集成电路） 窗口功能提供给系统，并且通过虚拟窗口执行来自前端和/或后端的I / O，从而增加数据完整性代码并执行数据的自动双重写入。 在这种存储控制装置中设置有作为CS / DS（代码存储/数据存储）和高速缓存的组合的电池备份存储器，实现了对块数据的保护以及双重写入高速缓存（用户 数据，控制数据），以便在数据输入/输出控制时保持可靠性。

公开(公告)号：EP2182443B1

公开(公告)日：2011-08-03

申请号：EP09251131.0

申请日：2009-04-20

Applicant: Hitachi Ltd.

Inventor： Tanaka, Katsuya ,  Shimada, Kentaro

IPC: G06F11/20

CPC classification number: G06F11/201

公开(公告)号：EP2365428A1

公开(公告)日：2011-09-14

申请号：EP11169084.8

申请日：2006-11-10

Applicant: Hitachi Ltd.

Inventor： Tanaka, Katsuya ,  Shimada, Kentaro

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0601 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: A storage system (100) using flash memories includes a storage controller (SC) and plural flash memory modules (Pxx) as storage media. Each flash memory module includes at least one flash memory chip (MEM) and a memory controller (MC) for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract translation: 使用闪存存储器的存储系统（100）包括存储控制器（SC）和多个闪存存储器模块（地址Pxx）作为存储介质。 每个闪存存储器模块包括至少一个闪存存储器芯片（MEM）和对于属于闪速存储器芯片块的找平擦除计数的存储器控​​制器（MC）。 存储控制器结合了多个闪存存储器模块成第一逻辑组，反酸酯用于访问属于第一逻辑组，以用于处理在所述存储控制器中的第一地址的第二地址的闪存存储器模块的第一地址，并组合 多个第一逻辑组成第二逻辑组。

公开(公告)号：EP1586986A2

公开(公告)日：2005-10-19

申请号：EP04030004.8

申请日：2004-12-17

Applicant: Hitachi, Ltd.

Inventor： Fujimoto, Kazuhisa ,  Hosoya, Mutsumi ,  Watanabe, Naoki ,  Shimada, Kentaro

IPC: G06F3/06

CPC classification number: G06F12/0866 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0661 ,  G06F3/067 ,  G06F12/0813

Abstract: To provide a storage system with a cost/ performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units (10) and data caching control units (21) are connected to each other through an interconnection (31), the data caching control units (21) are divided into plural control clusters (70), each of the control clusters including at least two or more data caching control units (21), control of a cache memory (111) is conducted independently for each of the control clusters (70), and one of the plural data caching control units (21) manages, as a single system; protocol transformation units (10) and the plural control clusters (70) based on management information stored in a system management information memory unit (160).

Abstract translation: 提供符合系统规模（从小规模到大规模配置）的性价比的存储系统。 在存储系统中，协议转换单元（10）和数据高速缓存控制单元（21）通过互连（31）彼此连接，数据高速缓存控制单元（21）被划分成多个控制簇（70），每个 在包含至少两个以上的数据高速缓存控制部（21）的控制集群中，对每个控制集群（70）独立地进行高速缓冲存储器（111）的控制，多个数据高速缓存控制部（21 ）作为一个单一的系统管理; 基于管理信息存储在系统管理信息存储单元（160）中的协议转换单元（10）和多个控制集群（70）。

公开(公告)号：EP2365428B1

公开(公告)日：2013-05-08

申请号：EP11169084.8

申请日：2006-11-10

Applicant: Hitachi Ltd.

Inventor： Tanaka, Katsuya ,  Shimada, Kentaro

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0601 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7208 ,  G06F2212/7211

公开(公告)号：EP2182443A1

公开(公告)日：2010-05-05

申请号：EP09251131.0

申请日：2009-04-20

Applicant: Hitachi Ltd.

Inventor： Tanaka, Katsuya ,  Shimada, Kentaro

IPC: G06F11/20

CPC classification number: G06F11/201

Abstract: The present invention relates to a storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) "VF 0:0, 1" of each endpoint device (EDO-ED2) from a root port RP0. Likewise, "VF 1:0, 1" of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to EDO in a normal state, "VF 0:0, 1" and "MVP 0, 0" are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to EDO, "VF 1:0, 1" and "MVF 0, 0" are connected by VF mapping. As a result, failover to the second data path is realized.

Abstract translation: 本发明涉及其中所述MR-IOV是施加到一个存储控制器的内部网络的存储装置。 数据路径故障切换可以在存储装置中执行。 所述存储控制器的内部网络被配置为使得一个虚拟功能（VF）“VF 0：0,1”的访问从根端口RP0每个端点设备（EDO-ED2）的。 同样地，“VF 1：0,1”每个端点设备可以从根端口RP1进行访问。 在从RP0至EDO在正常状态下的第一数据路径，“VF 0：0,1”和“MVP 0,0”通过VF映射连接。 当第一数据路径上发生了故障的，则MR-PCIM执行VF迁移，由此在从RP1到EDO，“VF 1：0,1”第二数据路径和“MVF 0,0”通过VF连接 映射。 其结果是，故障转移到第二数据路径实现。