公开(公告)号：WO02078082A3

公开(公告)日：2003-02-27

申请号：PCT/GB0201414

申请日：2002-03-25

Applicant: IBM ,  IBM UK

Inventor： ADAMS CHARLOTTE ,  STAMPER ANTHONY

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/7684

Abstract: A method for fabricating a dual damascene coper interconnect which electrically contacts a damascene tungsten wiring level (190) comprising forming a first layer on a semiconductor substrate, a silicon nitride layer (140) on the first layer, and a silicon dioxide layer (150) on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by electrically insulating material. A continuous space (630) is formed by etching two contact throughs (910) through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact throughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

Abstract translation: 一种用于制造电接触镶嵌钨布线层（190）的双镶嵌辅助器互连的方法，包括在半导体衬底上形成第一层，在第一层上形成氮化硅层（140），以及二氧化硅层（150） 在氮化硅层上。 第一层包括由电绝缘材料隔开的镶嵌钨互连区域。 通过蚀刻通过二氧化硅和氮化硅层的两个接触通孔（910）以暴露镶嵌钨互连区域以及通过蚀刻两个接触通孔之间的二氧化硅层的顶部而形成连续空间（630）。 二氧化硅层的缩小部分保留在两个接触槽之间。 连续的空间填充有镶嵌铜。 所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。

公开(公告)号：JP2008135758A

公开(公告)日：2008-06-12

申请号：JP2007316113

申请日：2007-12-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ADAMS CHARLOTTE ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/7684

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for establishing reliable, low-resistance connection between damascene copper wiring of upper level and damascene tungsten wiring of lower level.
SOLUTION: A method for forming a dual-damascene copper interconnect portion 120, that is connected to damascene tungsten wiring at a lower level comprises a step of forming a first layer 90, which includes tungsten interconnect regions, electrically insulated by an insulating material on a semiconductor substrate 110; a step of forming a silicon nitride layer on the first layer 90, and a silicon dioxide layer 150 on the silicon nitride layer; a step of forming a continuous space, by etching two connection troughs passing through the silicon dioxide layer and the silicon nitride layer to expose the underlying tungsten interconnect regions and by etching a top portion of the silicon dioxide layer between the two connection troughs to reduce sharp edges of the silicon dioxide layer between the two connection troughs; and a step of filling the continuous space with damascene copper, to electrically connect the dual damascene copper interconnect portion to the exposed underlying tungsten interconnect regions.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在上层的镶嵌铜布线和下层的镶嵌钨布线之间建立可靠的低电阻连接的方法和结构。 解决方案：用于形成双层镶嵌铜互连部分120的方法，其连接到较低级别的镶嵌钨布线包括形成第一层90的步骤，第一层90包括钨互连区域，其通过绝缘材料电绝缘 半导体衬底110上的材料; 在第一层90上形成氮化硅层的步骤和氮化硅层上的二氧化硅层150; 通过蚀刻通过二氧化硅层和氮化硅层的两个连接槽以暴露下面的钨互连区域并且通过蚀刻两个连接槽之间的二氧化硅层的顶部部分来形成连续空间的步骤，以减少锐利 两个连接槽之间的二氧化硅层的边缘; 以及用镶嵌铜填充连续空间的步骤，将双镶嵌铜互连部分电连接到暴露的下部钨互连区域。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2391388A

公开(公告)日：2004-02-04

申请号：GB0322556

申请日：2002-03-25

Applicant: IBM

Inventor： ADAMS CHARLOTTE ,  STAMPER ANTHONY

IPC: H01L21/3105 ,  H01L21/311 ,  H01L23/522 ,  H01L21/768

Abstract: A method for fabricating a dual damascene coper interconnect which electrically contacts a damascene tungsten wiring level (190) comprising forming a first layer on a semiconductor substrate, a silicon nitride layer (140) on the first layer, and a silicon dioxide layer (150) on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by electrically insulating material. A continuous space (630) is formed by etching two contact throughs (910) through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact throughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

公开(公告)号：GB2391388B

公开(公告)日：2005-10-26

申请号：GB0322556

申请日：2002-03-25

Applicant: IBM

Inventor： ADAMS CHARLOTTE ,  STAMPER ANTHONY

IPC: H01L21/3105 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768

Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.