公开(公告)号：GB2457126A

公开(公告)日：2009-08-05

申请号：GB0900660

申请日：2009-01-16

Applicant: IBM

Inventor： ARP ANDREAS ,  KOEHL JUERGEN ,  SALZ PHILLIP

IPC: G06F17/50

Abstract: An integrated circuit design, two or more functional blocks (which may be top-level functions in a hierarchical circuit design) are interconnected with auxiliary or spare connections. The proposed integrated circuit design allows change of an existing design through introduction of logical and/or physical changes of the underlying integrated circuit in a cost-and time-efficient manner. These additional connections, wiring and re-powering resources, as part of the global routing step, may lead to changes in the optimisation and congestion of the ic design to a certain limit, but the evaluation of where to insert connections will allow changes late in the design process. The insertion assessment may include pin assignment, signal, circuit definition and timing constraints. Point to point interconnections may be arranged over multiple levels of the hierarchical design, between edges or at functional block level and may be trees to allow one to many connection.

公开(公告)号：GB2457126B

公开(公告)日：2012-03-14

申请号：GB0900660

申请日：2009-01-16

Applicant: IBM

Inventor： ARP ANDREAS ,  KOEHL JUERGEN ,  SALZ PHILLIP

IPC: G06F17/50