公开(公告)号：JPH0992781A

公开(公告)日：1997-04-04

申请号：JP3173596

申请日：1996-02-20

Applicant: IBM

Inventor： VOLDMAN STEVEN HOWARD ,  BAKEMAN PAUL EVANS JR

IPC: H01L25/00 ,  G11C5/00 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a multichip semiconductor structure having an integrated circuit and a programmable circuit which protects the input-output nodes of chips from static discharge by providing the chips of a first semiconductor device and a second semiconductor chip electrically and mechanically coupled with each other in the multichip semiconductor structure. SOLUTION: A multichip semiconductor structure is provided with a first semiconductor chip having a first circuit which gives a prescribed circuit function and a second semiconductor chip which is electrically and mechanically coupled with the semiconductor chip. The second semiconductor chip has a second circuit which partially gives a circuit function to the first circuits. That is, a memory array chip 10 is provided wit memory arrays 12 which are divided from each other by a word decoder 14 for a word line having a tap at the center. The bit switch, sense amplifier, and driver 16 of the memory array 12 are arranged along the edge section 18 of the chip 10. The circuit 14 and driver 16 are called 'memory access circuits'.

公开(公告)号：JPH08250643A

公开(公告)日：1996-09-27

申请号：JP3153796

申请日：1996-02-20

Applicant: IBM

Inventor： VOLDMAN STEVEN HOWARD ,  BAKEMAN PAUL EVANS JR

IPC: H01L25/00 ,  H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To protect an inter-chip electrostatic discharge preventive multi-chip semiconductor structure from electrostatic discharge or the other excessive voltage which can damage the structure by a method, wherein first and second semiconductor device chips are laminated in such a way that the chips are provided in parallel to each other and the structure is provided with a discharge suppression means for coupling electrically both chips with each other. SOLUTION: A first power surface 10 of a chip (k) is coupled electrically with the second power surface 12 of a chip (t) via an inter-chip discharge suppression network Sii . A third power surface 14 of the chip (K) is coupled electrically with a fourth power surface 16 of the chip (t) via a second inter-chip discharge suppression network Sjj . A network 20 of the chip (k) is coupled between the surfaces 10 and 14, while the suppression network 20 of the chip (t) is coupled between the surfaces 12 and 16. By such inter-chip discharge suppression networks and the discharge suppression networks in the chips, discharge which is generated between the semiconductor device chips in a multi-chip stack, between a power supply surface and an external connection point, between an external connection point and a power supply surface and between the external connection points, can be suppressed.