-
公开(公告)号：GB2587948B
公开(公告)日：2021-11-24
申请号：GB202017634
申请日：2019-04-02
Applicant: IBM
Inventor： JAMES O'CONNOR , BARRY TRAGER , WARREN MAULE , MARC GOLLUB , BRAD WILLIAM MICHAEL , PATRICK JAMES MEANEY
Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
-
公开(公告)号：GB2576860B
公开(公告)日：2020-08-05
申请号：GB201918172
申请日：2018-06-14
Applicant: IBM
Inventor： PATRICK JAMES MEANEY , BARRY TRAGER , GLENN DAVID GILDA , ARTHUR O'NEILL JR
Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
-
公开(公告)号：GB2587948A
公开(公告)日：2021-04-14
申请号：GB202017634
申请日：2019-04-02
Applicant: IBM
Inventor： JAMES O'CONNOR , BARRY TRAGER , WARREN MAULE , MARC GOLLUB , BRAD WILLIAM MICHAEL , PATRICK JAMES MEANEY
IPC: G11C16/26
Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
-
公开(公告)号：GB2576860A
公开(公告)日：2020-03-04
申请号：GB201918172
申请日：2018-06-14
Applicant: IBM
Inventor： PATRICK JAMES MEANEY , BARRY TRAGER , GLENN DAVID GILDA , ARTHUR O'NEILL JR
Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
-
-
-
Search Results
4
records
(took 0.023 seconds)
