2.
    发明专利
    未知

    公开(公告)号:FR2401487A1

    公开(公告)日:1979-03-23

    申请号:FR7820118

    申请日:1978-06-29

    Applicant: IBM

    Inventor: BELSER KARL A

    Abstract: A major/minor loop bubble domain memory system maintains the non-volatility of data when subjected to a power on-off-on sequence. A bubble domain shift register is associated with the major/minor loop array and indicates when a block of data in the major loop is in position to be transferred into the minor loops. The length of the shift register is related to the propagation delay of the path over which a bubble is propagated along the major loop from a minor loop read transfer switch to the write transfer switch for the same minor loop.

    4.
    发明专利
    未知

    公开(公告)号:FR2274112A1

    公开(公告)日:1976-01-02

    申请号:FR7514035

    申请日:1975-04-29

    Applicant: IBM

    Inventor: BELSER KARL A

    Abstract: A method and apparatus for the point plotting and rearrangement of graphical data from a coded source into a buffer for raster type display. The execution of a graphic order in a stored program controllable graphics terminal are represented by a line generating a sequence of X Y coordinate values, which values are to be plotted or displayed. The points are plotted into a work organized memory array in the form of topologically adjacent rectangular subarrays. These subarrays are then transformed into linear arrays. In order to conserve memory they directly replace the previous topologically adjacent subarrays in the memory. The linear arrays may then be accessed a word at a time and applied to the raster display.

    NON-VOLATILE BUBBLE DOMAIN MEMORY SYSTEM

    公开(公告)号:CA1121052A

    公开(公告)日:1982-03-30

    申请号:CA303410

    申请日:1978-05-16

    Applicant: IBM

    Inventor: BELSER KARL A

    Abstract: NON-VOLATILE BUBBLE DOMAIN MEMORY SYSTEM A major/minor loop bubble domain memory system maintains the non-volatility of data when subjected to a power on-off-on sequence. A bubble domain shift register is associated with the major/minor loop array and indicates when a block of data in the major loop is in position to be transferred into the minor loops. The length of the shift register is related to the propagation delay of the path over which a bubble is propagated along the major loop from a minor loop read transfer switch to the write transfer switch for the same minor loop.

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