公开(公告)号：BR7702817A

公开(公告)日：1978-02-28

申请号：BR7702817

申请日：1977-05-02

Applicant: IBM

Inventor： BOUKNECHT M ,  BOURKE D ,  VERGARI L

IPC: G06F13/12 ,  G06F9/46 ,  G06F13/34 ,  G06F3/04

Abstract: Improvements introduced in a peripheral device control unit with improved counting logic, for use in a data processing system including a central processing unit, a memory unit, a logic input-output control unit and a line general coupling (i/f). (Machine-translation by Google Translate, not legally binding)

公开(公告)号：BR7702819A

公开(公告)日：1978-04-04

申请号：BR7702819

申请日：1977-05-02

Applicant: IBM

Inventor： PUTTLITZ F ,  BOURKE D

IPC: G06F12/14 ,  G06F9/34 ,  G06F12/02 ,  G06F12/06 ,  G06F9/06

Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.

公开(公告)号：BR7702816A

公开(公告)日：1978-02-21

申请号：BR7702816

申请日：1977-05-02

Applicant: IBM

Inventor： BOURKE D ,  PE VERGARL L

IPC: G06F13/10 ,  G06F13/34 ,  G06F3/04

Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

公开(公告)号：BR7908412A

公开(公告)日：1980-10-07

申请号：BR7908412

申请日：1979-12-20

Applicant: IBM

Inventor： MADRUGA L ,  MENDELSON R ,  BOURKE D

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F9/22 ,  G06F13/08

公开(公告)号：BR7702777A

公开(公告)日：1978-02-28

申请号：BR7702777

申请日：1977-05-02

Applicant: IBM

Inventor： BOURKE D

IPC: G06F12/02 ,  G06F9/06

Abstract: Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory.