公开(公告)号：CA1205148A

公开(公告)日：1986-05-27

申请号：CA441050

申请日：1983-11-14

Applicant: IBM

Inventor： BLUMBERG RICHARD J ,  BRENNER STEWART ,  ROBORTACCIO ROCCO J

IPC: H03K19/013 ,  H03K19/088

Abstract: Improved TTL Logic Circuit Disclosed is the addition of passive feedback to a prior art T2L circuit The T2L circuit with feedback, in accordance with the invention, has a lower power dissipation while retaining noise immunity and small gate delay. The additional resistor required for the feedback T2L circuit, in accordance with the invention, can be incorporated into the T2L cell without increasing the cell size. The feedback T2L circuit, in accordance with the invention, lends itself to the addition of an integrated direct-coupled inverter (DCI) function. The feedback T2L circuit, in accordance with the invention, permits more function to be placed on an integrated circuit semiconductor chip while maintaining gate performance and adherence to power restrictions.

公开(公告)号：DE3376375D1

公开(公告)日：1988-05-26

申请号：DE3376375

申请日：1983-11-29

Applicant: IBM

Inventor： BLUMBERG RICHARD JAY ,  BRENNER STEWART ,  ROBORTACCIO ROCCO JOSEPH

IPC: H03K19/013 ,  H03K19/088

Abstract: Improved TTL circuits are disclosed which have an additional element (R4) to obtain passive resistive feedback which results in a reduction of power dissipation for a given speed (delay). Depending on the arrangement, the feedback may be either full or partial. The additional element can be incorporated in a TTL cell without increasing the cell size. Due to reduced power dissipation, a higher packing density may be achieved on a semiconductor integrated circuit chip.