公开(公告)号：CA1151326A

公开(公告)日：1983-08-02

申请号：CA372089

申请日：1981-03-02

Applicant: IBM

Inventor： ALVAREZ JOSEPH A III ,  BENSADON JOSEPH M ,  BRENNEN JOHN F ,  BRICKMAN NORMAN F ,  KRUG ROBERT W

IPC: H04J3/06 ,  H04B7/15 ,  H04B7/185 ,  H04B7/212 ,  H04B7/26 ,  H04L23/00

Abstract: MECHANISM FOR SYNCHRONIZATION OF DATA PORTS IN TDMA COMMUNICATION The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This eliminates the necessity for bit stuffing to accommodate non-integral multiple data rate data ports and yet allows data activity compression operations to be carried out. MA9-79-006

公开(公告)号：CA1220832A

公开(公告)日：1987-04-21

申请号：CA455135

申请日：1984-05-25

Applicant: IBM

Inventor： BENSADON JOSEPH M ,  BRICKMAN NORMAN F

IPC: H04L29/02 ,  H04B7/15 ,  H04B7/212 ,  H04Q11/04 ,  H04J3/02

Abstract: X.21 Switching System A system is disclosed to provide X.21 in-band call establishment signaling in the data path of a data communication system in a satellite communications controller. The system includes an X.21 signaling protocol between a data terminal equipment and the satellite communications controller on the terrestrial side and allows self-switched digital data port functions in lieu of associated voice port and line functions as practiced in the prior art. An important aspect is that the signaling rate is the same as the line data rate. At the start of the signaling state, the E input to the call processor is activated for the appropriate port. Call establishment signals are then processed through the digital switch and an X.21 adapter to the system's control processor. Finally the call establishment signaling has been completed and all data bits go through the digital switch and are transmitted to the digital interface. At the end of the call the data port goes back to the first, idle state. MA9-82-014

公开(公告)号：CA1079852A

公开(公告)日：1980-06-17

申请号：CA260566

申请日：1976-09-03

Applicant: IBM

Inventor： BRICKMAN NORMAN F ,  LOGUE JOSEPH C

IPC: G11C15/04 ,  H03K19/177 ,  H03K19/20 ,  G11C11/40

Abstract: SIMPLIFIED DYNAMIC ASSOCIATIVE CELL This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line; with their emitters either left floating or connected to an input line carrying either true or complement of one variable; and with their bases either connected to an input line carrying the true or complement of a second variable or to the output line which is maintained at a fixed potential. This permits the performing of sixteen different logic functions of the two input variables by the cell.