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    2.
    发明专利
    未知

    公开(公告)号：DE2356260A1

    公开(公告)日：1974-05-30

    申请号：DE2356260

    申请日：1973-11-10

    Applicant: IBM

    Inventor： BROWN DAVID TRENT

    IPC: G11C19/00 ,  G06F7/78 ,  G06F12/00 ,  G11C19/08

    Abstract: 1398204 Digital data storage INTERNATIONAL BUSINESS MACHINES CORP 10 Sept 1973 [16 Nov 1972] 42404/73 Addition to 1313444 Heading G4C [Also in Division H3] The data storage system of the parent Specification 1,313,444, in which address bits a and data bits d of pages of data are stored in shift registers having recirculation loops L1 and L2 respectively including and excluding the read/ write access position K, is modified in that one bit (e.g. the lowest order) of a requested page address is used to control the direction of shifting so as to reduce the access time. Recently accessed pages are maintained in positions for successive shifting into the access position K in preference to other pages, the arrangement described storing pages with even-numbered addresses at the right-hand end of the registers and those with odd-numbered addresses at the left-hand end. The address of a requested page is supplied over lines 118, the lowest order address bit determining the direction of shift signals produced by a shift control unit until a comparator ACU detects a match, whereupon the shift control unit is conditioned for shifting in the opposite direction to restore the pages to the order of most recent access leaving the last accessed page in position K. The number of shifts required to access the desired page is counted in a reversible counter 200 which controls the number of shifts which take place in the restore operation in conjunction with a latch 310 which is set by the lowest order address bit. Magnetic bubble shift registers are described for use in the system, the shift control unit supplying a reversible rotating magnetic field to effect shifting in the registers. The use of FET registers is also mentioned.

    DATA STORES
    5.
    发明专利
    DATA STORES 未知

    公开(公告)号：AU3930572A

    公开(公告)日：1973-08-30

    申请号：AU3930572

    申请日：1972-02-23

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  BROWN DAVID TRENT ,  WALKER ERNEST LEE

    IPC: G06F7/78 ,  G11C19/08 ,  G11C19/00 ,  H03K23/24 ,  G11C11/14

    Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

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