公开(公告)号：GB2505140A

公开(公告)日：2014-02-19

申请号：GB201321837

申请日：2012-05-21

Applicant: IBM

Inventor： FLANAGAN JOHN ,  TURNER JEFFREY ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS ,  KUCH GEORGE PETER ,  HIGGS RAYMOND MICHAEL

IPC: G06F13/38

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

公开(公告)号：GB2505592A

公开(公告)日：2014-03-05

申请号：GB201321241

申请日：2012-05-17

Applicant: IBM

Inventor： FLANAGAN JOHN ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS

IPC: G06F13/38

Abstract: On embodiment includes a computer program product for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating addressing information and forwarding the addressing information from at least one channel to a network interface between the channel subsystem and at least one I/O device, the addressing information specifying a location in a local channel memory; forwarding an I/O command message to the at least one I/O device via the network interface; responsive to the I/O command message, receiving a data transfer request from the network interface that includes the addressing information; responsive to receiving the data transfer request, accessing one of a plurality of address control words (ACWs), each ACW specifying an address of a location in a host computer memory; and routing the data transfer request to the host memory location specified in the ACW.

公开(公告)号：GB2491438A

公开(公告)日：2012-12-05

申请号：GB201206682

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38

Abstract: Method for input/output (I/O) between host computer and control-unit 118, comprising: generating and storing in local memory 132 address control words specifying host memory 106 locations for data transfer and data check word generation and save field; responsive to data transfer requests including data to be stored in host memory and data check word, storing data-check-word in save field, and checking data corruption; responsive to data-transfer requests for data to be retrieved from host memory, generating data-check-words based on generation field and appending data-check-words to data. Data-check-words include: longitudinal (LRC)/ cyclical (CRC) redundancy check-word and checksum. I/O can be transport mode. I/O start rates are increased and response time reduced by providing data router 160 in channel of a channel subsystem allowing host bus adaptor (HBA) 154 to directly access host memory without storing I/O data in channel. Isolation for error checking and addressing of multiple address spaces is provided.

公开(公告)号：GB2491438B

公开(公告)日：2014-10-22

申请号：GB201206682

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  BUBB CLINTON ,  FLANAGAN JOHN R

IPC: G06F13/12 ,  G06F13/38

公开(公告)号：GB2491439A

公开(公告)日：2012-12-05

申请号：GB201206683

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/42 ,  G06F13/12

Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and having an expected offset filed (264, Fig 11) indicating a relative order of an expected data transfer request is stored in the local memory. An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW includes an offset field (180, Fig 5) indicating a relative order or a corresponding data transfer request relative to other data transfers in the plurality of consecutive data transfer requests. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information. A data route in the channel compares the offset and expected offset fields to determine if the transfer request has been received in the correct order. If the request has been received in order, the corresponding ACW is accessed retrieved and used to route the data transfer request to the host memory (106) specified in the ACW. The expected offset field in the ACW is incremented by an amount corresponding to a size of the data transfer request.

公开(公告)号：GB2505140B

公开(公告)日：2014-06-04

申请号：GB201321837

申请日：2012-05-21

Applicant: IBM

Inventor： FLANAGAN JOHN ,  TURNER JEFFREY ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS ,  KUCH GEORGE PETER ,  HIGGS RAYMOND MICHAEL

IPC: G06F13/38

公开(公告)号：GB2491439B

公开(公告)日：2013-05-15

申请号：GB201206683

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/42 ,  G06F13/12

Abstract: A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW.

公开(公告)号：GB2491437A

公开(公告)日：2012-12-05

申请号：GB201206681

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38

Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and including a field for storing header information for use in one or more messages transmitted between the channel subsystem and the control unit. An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information. In response to a data store request including a header the data is routed to the memory location stored in the ACW and the header stored in the corresponding ACW. In response to a data read request including a header the data is retrieved from the host memory location specified in the ACW and header information is appended to the data.

公开(公告)号：GB2491436A

公开(公告)日：2012-12-05

申请号：GB201206680

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F21/00

Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and having an error checking field is stored in the local memory. An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information. A data route in the channel compares the ACW error checking field and the address control structure error checking field and if they match, the corresponding ACW is retrieved and used to route the data transfer request to the host memory (106) specified in the ACW.

公开(公告)号：GB2505592B

公开(公告)日：2014-08-06

申请号：GB201321241

申请日：2012-05-17

Applicant: IBM

Inventor： FLANAGAN JOHN ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS

IPC: G06F13/38

Abstract: On embodiment includes a computer program product for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating addressing information and forwarding the addressing information from at least one channel to a network interface between the channel subsystem and at least one I/O device, the addressing information specifying a location in a local channel memory; forwarding an I/O command message to the at least one I/O device via the network interface; responsive to the I/O command message, receiving a data transfer request from the network interface that includes the addressing information; responsive to receiving the data transfer request, accessing one of a plurality of address control words (ACWs), each ACW specifying an address of a location in a host computer memory; and routing the data transfer request to the host memory location specified in the ACW.