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    CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION
    1.
    发明申请
    CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION 审中-公开
    具有减少面积和功耗的DFE的电路和方法

    公开(公告)号：WO2010089170A2

    公开(公告)日：2010-08-12

    申请号：PCT/EP2010050286

    申请日：2010-01-12

    Applicant: IBM ,  IBM UK ,  KIM BYUNGSUB ,  BULZACCHELLI JOHN FRANCIS

    Inventor： KIM BYUNGSUB ,  BULZACCHELLI JOHN FRANCIS

    IPC: H04L25/03

    CPC classification number: H03K3/35613 ,  H03K3/012 ,  H03K3/356139 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L2025/0349

    Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to 10 multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

    Abstract translation: 1 / n速率判决反馈均衡器（DFE）和方法包括多个分支。 每个分支包括一个加法电路，其被配置为向接收到的输入添加反馈信号，以及锁存器，被配置为根据时钟信号接收加法电路的输出。 反馈电路包括被配置为接收每个分支的输出作为输入的多路复用器，所述多路复用器具有时钟选择输入，并且被配置为对多个分支的输出进行多路复用以组合全速比特序列，以及被配置为提供消除的滤波器 来自接收输入的符号间干扰（ISI）提供给每个分支的夏季电路。

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