公开(公告)号：DE2725396A1

公开(公告)日：1978-01-05

申请号：DE2725396

申请日：1977-06-04

Applicant: IBM

Inventor： CAMPBELL JOHN EDWARD ,  THOMPSON GERHARD ROBERT

IPC: G11C7/00 ,  G06F5/06 ,  G06F12/12 ,  H03M7/16 ,  G11C9/00 ,  G06F13/06

Abstract: 1533831 FIFO storage INTERNATIONAL BUSINESS MACHINES CORP 13 June 1977 [2 July 1976] 24608/77 Heading G4A Each storage area 0-7 has a marker bit a-h, an encoding (EXOR) circuit 10 produces from the marker bits an indication of which storage area was the first to be loaded, and each time a storage area is loaded its marker bit is inverted, whereby the encoding circuit identifies the storage areas in a predetermined cyclic sequence. The encoding circuit shown produces coded bit combinations ABC in Gray code sequence when the marker bits are set from 0 to 1 in the order a, b, d, c, g, h, f, e and are subsequently reset from 1 to 0 in the same order as successive storage areas are loaded (overwriting occurring after the first sequence). The FIFO store may form the cache memory of a multilevel storage system, the output of circuit 10 being decoded to select the storage area to receive replacement data from main storage when the requested data is not present in the cache.