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公开(公告)号：US3665418A
公开(公告)日：1972-05-23
申请号：US3665418D
申请日：1968-07-15
Applicant: IBM
CPC classification number: G06F11/2007
Abstract: Status switching means for an automatically repaired computer system of the stand-by redundancy type adapted to replace a failed component by a stand-by spare, characterized in that the switching means include separate selection or switch means associated with each data receiving device, respectively, so that there is no sharing of a given selection means between different receiving devices, whereby no selection means constitutes a ''''hard core'''' component the failure of which would interrupt computer operation. By the operation of encoded control means, a reconfiguration of the switching system is effected to shift around a faulty component.
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公开(公告)号：DE2554945A1
公开(公告)日：1976-07-08
申请号：DE2554945
申请日：1975-12-06
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL
Abstract: Apparatus for a digital memory system which performs single and double error detection and correction, as well as the detection of faults in the memory storage elements which do not produce errors in the data word stored therein. The data word is encoded in a specialized Hamming SEC/DED code and the apparatus generates syndromes and byte parity bits which are analyzed to detect both the presence and nature of the errors and faults. A parallel correction procedure is followed and the results thereof compared to prevent the erroneous correction of errors.
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Patent Agency Ranking
公开(公告)号：DE2329306A1
公开(公告)日：1974-01-10
申请号：DE2329306
申请日：1973-06-08
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL , WADIA ASPI BAMANSHAW
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公开(公告)号：DE2327352A1
公开(公告)日：1974-01-10
申请号：DE2327352
申请日：1973-05-29
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL , WADIA ASPI BAMANSHAW
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公开(公告)号：DE2320354A1
公开(公告)日：1973-11-15
申请号：DE2320354
申请日：1973-04-21
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL , HSIEH EDWARD PO-CHIU , WADIA ASPI BAMANSHAW
Abstract: Novel error correction and detection codes and self-checking translators therefor are disclosed. A first of these codes is a t b-adjacent bit group error correcting and t+d b-adjacent d-adjacent bit group error detecting code using a quantity of 2t+d groups of b check bits. This code with a b-bit BSM (basic storage module) memory organization is capable of correcting b-adjacent errors due to failures in any t basic storage modules, detecting b-adjacent errors due to failures in any t+d basic storage modules, and, because of the translator design, detecting with high probability b-adjacent errors in 2t+2d-1 storage modules where 1
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公开(公告)号：DE2317576A1
公开(公告)日：1973-11-08
申请号：DE2317576
申请日：1973-04-07
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL , HSIEH EDWARD PO-CHIU , WADIA ASPI BAMANSHAW
Abstract: There is disclosed a switching arrangement for effecting storage module reconfiguration in a data processing system wherein the memory comprises a quantity q of operating n-bit/BSM's (basic storage modules) and a quantity s of spare n-bit/BSM's. The arrangement comprises an input status register means which in turn comprises an input status register associated with each of the BSM's respectively, which control an input reconfiguration network, and an output status register means which comprises an output status register respectively associated with each of the BSM's, which control an output reconfiguration network. The input and output status registers and the input and output reconfiguration networks are of like structures, respectively. Initially, in normal operation, the operating BSM's are connected to respective bit positions and all of the input and output status registers assume a chosen initial state. Initially, upon the ascertaining from a diagnosis, for example, that one of the operating BSM's has failed, the input status register with which the failed BSM is associated is forced to a parity state opposite from the normal operating parity state, and all of the input status registers succedding in designated numerical value are switched to a next state. This causes the failed BSM to be disconnected from the input; the input originally connected to the failed BSM is connected to the BSM of succeeding higher value, the next higher input connected to the next BSM and so on until the last input is connected to the first pare BSM. At this point, all of the contents of the memory, i.e., the initially operating BSM's, are passed through the output reconfiguration network under the control of the output status registers (which is not yet altered) and through a correction circuit wherein there is provided means for applying an error correction code. The memory contents are then passed from the correction circuit back into the present operating BSM's through the input reconfiguration network under the control of the input status registers. Thereafter, the contents of the output status registers are then brought into conformity with the present contents of the input status registers whereupon normal operation can resume. The arrangement permits as many changes in the contents, i.e., states of the status registers after their initial states as there are spare BSMM's in the memory organization, the contents of status registers of operating BSM's which succeed a failed BSM being switched to a next state. Suitably, an operating parity state of a status register is of even parity and, when its associated BSM fails, its state is forced to an odd parity. An algorithm is presented for diagnosing as a failed BSM which is based upon the criterion of the ascertaining of a bit position which has undergone corrections most frequently over a chosen period of time.
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公开(公告)号：GB1293488A
公开(公告)日：1972-10-18
申请号：GB1781071
申请日：1971-05-28
Applicant: IBM
Inventor： CARTER WILLIAM CASWELL , DUKE KEITH ALBERT , JESSEP DONALD CYRIL JR
IPC: G06F11/10
Abstract: 1293488 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 28 May 1971 [30 June 1970] 17810/71 Heading G4A Parity coded data is converted into error detecting/correcting coded data during a memory write access, and the same equipment is used during a memory read access to convert error detecting/correcting coded data into parity coded data. Memory write access.-Information comprising data bytes and byte parity bits is loaded into registers MR, MDR from a CPU. The parity of each byte in MDR is checked by XOR circuits in the error detect mechanism to produce a word for storage in a syndrome (S) register which should, e.g. be all 1's. If a parity error is detected an output on line 140 initiates a conventional interrupt to cause re-transmission or entry into a diagnostic or error routine. If the word in the S register is correct, the contents of register MR pass through a connection matrix in which selected groups of bits each contain one parity bit, to a set of XOR trees deriving a set of error detecting/correcting Hamming check bits on cable 120. These check bits are combined with the data bytes on cable 122 and gated at 124 by the " no error " signal 126 into register MDR to replace the parity coded data supplied by the CPU. Finally, at the end of the clock pulse controlling transfer to MDR, a " data valid " signal on line 134 effects transfer from MDR to memory. Memory read access.-Data bytes and associated Hamming check bits read out from memory are loaded into register MR. The contents of MR pass through the connection-matrix, which this time includes one check bit in each selected group of bits, to the XOR trees to generate one parity bit for each byte on cable 120. These parity bits are combined with the data bytes on cable 122 and are gated at 124 into the MDR register. The parity of each byte is checked by the XOR circuits in the error detect mechanism, the resulting syndrome word being gated into the S register. If only one bit in the S register is a " 0 " this indicates a single error in a check bit and detection of this condition is used to correct the appropriate bit in the MDR register. A single data bit error is indicated by an odd number of " 0's " (more than one) in the S register, and syndrome decoders detect which bit is in error so as to complement the appropriate bit when the contents of MDR are gated out to MR. Finally, the contents of MR (corrected) are transferred to MDR via the connection matrix and XOR trees to produce the correct parity bits, and the parity coded word is transferred from MDR to CPU.
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