公开(公告)号：JP2001243166A

公开(公告)日：2001-09-07

申请号：JP2001003157

申请日：2001-01-11

Applicant: IBM

Inventor： OSTEN THOMAS JAMES ,  CECCHI DELBERT RAYMOND ,  GREGORY SCOTT STILL

IPC: G06F13/12 ,  G06F13/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a simple enclosure service using a high speed point-to point serial bus. SOLUTION: An enclosure service in a computer system comprising a host computer and at least one target device is supplied on a functional path, favorably a comparatively high-speed point-to-point serial bus between the host computer and at least one target device. At least one target device and the host computer respectively have a full power operation mode and an auxiliary power mode. The host computer generates the enclosure service command and transmits it, on the functional path, to at least one target device. At least one target device, even in the auxiliary power mode, can receive the enclosure service command and respond to it.

公开(公告)号：DE68916620D1

公开(公告)日：1994-08-11

申请号：DE68916620

申请日：1989-10-24

Applicant: IBM

Inventor： CECCHI DELBERT RAYMOND ,  PHAN VAN NGHIA

IPC: G01R31/317 ,  G01R31/30 ,  H03K19/00 ,  H03K19/086 ,  G06F11/26 ,  G01R31/28

Abstract: An ECL logic circuit uses a single resistor (R5) in place of separate current-source and emitter-follower resistors. A single tap connects a point (205) on this resistor to the ground bus, and the signal--output line (131) connects to this resistor by a contact which is separate from the contact (231) connecting the emitter of the output transistor (T4) to the resistor.

公开(公告)号：DE68916620T2

公开(公告)日：1995-01-12

申请号：DE68916620

申请日：1989-10-24

Applicant: IBM

Inventor： CECCHI DELBERT RAYMOND ,  PHAN VAN NGHIA

IPC: G01R31/317 ,  G01R31/30 ,  H03K19/00 ,  H03K19/086 ,  G06F11/26 ,  G01R31/28

Abstract: An ECL logic circuit uses a single resistor (R5) in place of separate current-source and emitter-follower resistors. A single tap connects a point (205) on this resistor to the ground bus, and the signal--output line (131) connects to this resistor by a contact which is separate from the contact (231) connecting the emitter of the output transistor (T4) to the resistor.

公开(公告)号：DE68916094T2

公开(公告)日：1995-01-12

申请号：DE68916094

申请日：1989-03-28

Applicant: IBM

Inventor： CECCHI DELBERT RAYMOND ,  SUN KIM HYUNG ,  MITBY JOHN STEVEN ,  SWART DAVID PETER ,  STANISIC BALSHA ROBERT ,  TUNG WU PHILIP

IPC: H03K5/02 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094

Abstract: A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage (21), clamping circuitry (22), an output stage (23) and feedback circuitry (26). The clamping circuitry (22) clamps the voltage level presented to the output stage (23) at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the GPI circuitry rises, feedback circuitry (26) feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the speci-fied voltage level from 1.51 and 2.2 volts. The feedback circuitry (26) contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry (26), and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage (23) thereby reducing noise on the power supply and ground lines. The feedback circuitry (26) uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage (23) as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry (24) that discharges the voltage level of the feedback circuitry (26) when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.

公开(公告)号：DE68916094D1

公开(公告)日：1994-07-21

申请号：DE68916094

申请日：1989-03-28

Applicant: IBM

Inventor： CECCHI DELBERT RAYMOND ,  SUN KIM HYUNG ,  MITBY JOHN STEVEN ,  SWART DAVID PETER ,  STANISIC BALSHA ROBERT ,  TUNG WU PHILIP

IPC: H03K5/02 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094

Abstract: A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage (21), clamping circuitry (22), an output stage (23) and feedback circuitry (26). The clamping circuitry (22) clamps the voltage level presented to the output stage (23) at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the GPI circuitry rises, feedback circuitry (26) feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the speci-fied voltage level from 1.51 and 2.2 volts. The feedback circuitry (26) contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry (26), and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage (23) thereby reducing noise on the power supply and ground lines. The feedback circuitry (26) uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage (23) as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry (24) that discharges the voltage level of the feedback circuitry (26) when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.