公开(公告)号：DE3277096D1

公开(公告)日：1987-10-01

申请号：DE3277096

申请日：1982-05-07

Applicant: IBM

Inventor： CHAO HU HUBERT ,  DENNARD ROBERT HEATH

IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  G11C11/24 ,  G11C11/40

Abstract: An FET dynamic RAM array has one-FET-device cells (4) each associated with a respective bit line portion, there being two bit line portions, each associated with a respective node (N2) of the sense amplifier (3) by two FET switches operated by V (TOP) and V (BOTTOM). Capacitors (6) in the cells are charged according to the information they store. Cells are accessed by raising the potential of a word line e.g. WORD n for the cell with capacitor Cn, 1. If at that time capacitor Cn+ 1, 1 stores a >, and if BIT LINE L (BOTTOM) is at ground, the drain-source voltage of the associated FET (5) may force it to conduct so that the stored information is lost. This is prevented by V (BOTTOM) turning off L (BOTTOM) while the potential on BIT LINE L (BOTTOM) is at the precharge level (approximately VDD caused by OPC. The array is single-polysilicon, in which portions of word lines are used as cell capacitor electrodes.