公开(公告)号：JP2000036200A

公开(公告)日：2000-02-02

申请号：JP15147199

申请日：1999-05-31

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  CHRISTOPHER DOUGLAS WEAIT

IPC: G11C11/401 ,  G01R31/28 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00 ,  G06F11/22 ,  G06F12/06 ,  G06F12/16

Abstract: PROBLEM TO BE SOLVED: To improve the performance of an integrated circuit chip by setting the chip to obtain its optimum performance every time the power of the chip is increased and supplying the setting to a chip control. SOLUTION: During a self test, a condition is applied to a DRAM core 102 by an SPBIST logic 104, a control signal 110 is given to a control logic 108 and control parameters are modified. Then, by incremeting the signal 110, an internal timing control reduces an SA timing and a faster access/time is achieved. Then, similar tests are repeated by a faster SA timing and the logic 104 increments the signal 110 whenever a predicted result is obtained. These tests are repeated until the tests are failed and the limit of the SAT timing is exceeded. Then, the last value of the signal 110, at which the test is satisfied, i.e., the optimum value of the chip is stored in an NVRAM 106.