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    DUAL STRAIN-STATE SiGe LAYERS FOR MICROELECTRONICS
    3.
    发明申请
    DUAL STRAIN-STATE SiGe LAYERS FOR MICROELECTRONICS 审中-公开
    用于微电子的双应变态SiGe层

    公开(公告)号：WO2004084264A3

    公开(公告)日：2004-11-11

    申请号：PCT/US2004005481

    申请日：2004-02-25

    Applicant: IBM ,  CHU JACK OON

    Inventor： CHU JACK OON

    IPC: H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/10 ,  H01L29/778

    CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/1054

    Abstract: A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.

    Abstract translation: 公开了具有张应变SiGe部分和压应变SiGe部分的应变结晶层。 应变结晶层在SiGe弛豫缓冲层的顶部上外延结合或生长，使得拉伸应变SiGe具有低于SiGe弛豫缓冲层的Ge浓度，并且压缩应变SiGe具有高于Ge浓度的Ge浓度 SiGe轻松缓冲器的性能。 应变晶体层和松弛缓冲层可以位于半绝缘体衬底的顶部或绝缘分隔层的顶部。 在一些实施例中，拉伸SiGe层是纯Si，并且压缩SiGe层是纯Ge。 拉伸应变SiGe层适合用于承载电子传导型器件，而压应变SiGe适合用于承载空穴传导型器件。 应变晶体层能够接种外延绝缘体或化合物半导体层。

    Ultra-scalable high-speed heterojunction vertical n-channel misfet and its method
    5.
    发明专利
    Ultra-scalable high-speed heterojunction vertical n-channel misfet and its method 有权
    超高可靠性高速异步垂直N沟道MISFET及其方法

    公开(公告)号：JP2005012214A

    公开(公告)日：2005-01-13

    申请号：JP2004175740

    申请日：2004-06-14

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： OUYANG QIQING CHRISTINE ,  CHU JACK OON

    IPC: H01L21/20 ,  H01L21/336 ,  H01L29/12 ,  H01L29/165 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/7781 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/78687

    Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the strained vertical channel of the field effect transistor in which a drain region, main body region, and source region are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the field effect transistor and the source region and vertical channel independently form lattice strains to the main body region. The drain region contains a carbon-doped region to prevent the diffusion of a dopant (boron) into the main body region. When this invention is used, the problem about the leakage current from the source region due to the heterojunction and lattice strains is reduced. Apart from the leakage current, a lattice strain can be formed in a channel region for increasing mobility by selecting the semiconductor material. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供一种金属 - 绝缘体 - 半导体场效应晶体管（MISFET），其由在电流的流动方向上不存在异质势垒的导电沟道和源极/漏极与主体之间的异质结构成 体（体）晶体管。 解决方案：场效应晶体管的应变垂直沟道的结构，其中漏极区域，主体区域和源极区域结合在垂直单晶半导体结构的侧壁中，场效应晶体管， 并描述了CMOS电路和沟道，晶体管和电路的形成方法。 在场效应晶体管的源极和主体之间形成异质结，并且源极区和垂直沟道独立地形成到主体区域的晶格应变。 漏极区域包含碳掺杂区域，以防止掺杂剂（硼）扩散到主体区域中。 当使用本发明时，由于异质结和晶格应变引起的来自源极区的漏电流的问题减少了。 除了漏电流之外，通过选择半导体材料，可以在通道区域中形成晶格应变以增加迁移率。 版权所有（C）2005，JPO＆NCIPI

    Low-leakage heterojunction vertical transistor and its high-performance device
    6.
    发明专利
    Low-leakage heterojunction vertical transistor and its high-performance device 有权
    低泄漏异常垂直晶体管及其高性能器件

    公开(公告)号：JP2005012213A

    公开(公告)日：2005-01-13

    申请号：JP2004175642

    申请日：2004-06-14

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： OUYANG QIQING CHRISTINE ,  CHU JACK OON

    IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/12 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/778 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828

    Abstract: PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the vertical channel 165 of the field effect transistor in which a drain region 162, main body region 163, and source region 164 are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the transistor and the source region 164 and vertical channel 165 independently form lattice stains to the main body region 163. The drain region 162 contains a carbon-doped region to prevent the diffusion of dopants (namely, boron (B) and phosphorus (P)) into the main body region 163. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供一种绝缘栅半导体场效应晶体管（MISFET），其由在电流的流动方向上不存在异质势垒的导电沟道和源极/漏极与主体之间的异质结构成 （体积）的晶体管。 解决方案：场效应晶体管的垂直沟道165的结构，其中漏极区162，主体区163和源极区164结合在垂直单晶半导体结构的侧壁中，场 描述了效应晶体管和CMOS电路以及沟道，晶体管和电路的形成方法。 在晶体管的源极和主体之间形成异质结，并且源极区域164和垂直沟道165独立地形成到主体区域163的晶格斑。漏极区域162包含碳掺杂区域以防止掺杂剂的扩散（ 即硼（B）和磷（P））进入主体区域163.版权所有（C）2005，JPO＆NCIPI

    SILICON HAVING BULK AND STRAIN ON INSULATOR USING LOCAL SELECTION OXIDATION
    8.
    发明专利
    SILICON HAVING BULK AND STRAIN ON INSULATOR USING LOCAL SELECTION OXIDATION 失效

    公开(公告)号：JPH11284065A

    公开(公告)日：1999-10-15

    申请号：JP29372098

    申请日：1998-10-15

    Applicant: IBM

    Inventor： CHU JACK OON ,  ISMAIL KHALID EZZELDIN ,  LEE KIM YANG ,  OTT JOHN ALBRECHT

    IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To form buried oxide regions below regions of a single crystal semiconductor layer, by selecting a single crystal Si substrate, and forming a first SiGe epitaxial layer having a const. or gradient and first oxidation rate on the top face of the substrate. SOLUTION: A single crystal Si or SiGe substrate is selected, a first Si1-x Gex or (Si1-x Gex )a C1-a epitaxial layer 16 having a const. or gradient is formed on the top face 15 of the substrate 14 and has a first oxidation rate at specified temp. and ambient condition. The ambient condition includes O, water vapor or HCl or both. The const. or gradient compsn. of the epitaxial layer 16 needs the epitaxial growth, even if the lattice consts. of the layers 14 and 16 differ, and is selected so as to have the first oxidation rate.

    HIGH TEMP. SUPERCONDUCTOR STRUCTURE USING SI/SIGE
    9.
    发明专利
    HIGH TEMP. SUPERCONDUCTOR STRUCTURE USING SI/SIGE 失效

    公开(公告)号：JPH1093151A

    公开(公告)日：1998-04-10

    申请号：JP22490897

    申请日：1997-08-21

    Applicant: IBM

    Inventor： CHU JACK OON ,  ISMAIL KHALID EZZELDIN ,  LEE KIM YANG

    IPC: H01L39/22 ,  H01L29/161 ,  H01L29/165 ,  H01L29/80 ,  H01L39/02 ,  H01L39/12 ,  H01L39/24

    Abstract: PROBLEM TO BE SOLVED: To provide a superconducting structure, having a gate conformed with the conventional Si technology which enables or invalidate the superconduction state by changing the gate voltage to change the electron-to-hole ratio. SOLUTION: A structure which allows superconducting current to flow comprises a substrate, a first epitaxial p-type semiconductor layer 24 subjected to a compression strain for transferring 12, 14, 20 holes, a second epitaxial barrier layer 30 on the first layer, and a third epitaxial n-type semiconductor layer 32 subjected to a tensile strain for transferring electrons. The barrier layer 30 has sufficient thickness to limit the recombination of electrons but is sufficiently thin to form electron-hole pairs, due to the attraction between the electron and hole. The first and second layers has SiGe, e.g. Si1-x Gex , where x=0.6-0.8 for the first layer and x=0.3-0.4 for the second layer and third layer has Si.

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