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公开(公告)号：FR2304963A1
公开(公告)日：1976-10-15
申请号：FR7602997
申请日：1976-01-29
Applicant: IBM
Inventor： COOMBES DANIEL J , MESSINA BENEDICTO U
Abstract: 1484235 Memory paging; fault handling INTERNATIONAL BUSINESS MACHINES CORP 12 Feb 1976 [20 March 1975] 05513/76 Heading G4A In a storage system comprising a plurality of units, e.g. sections 1 to 4 of a high speed buffer 11, Fig. 1, which are used in a random sequence, a binary code reflecting the most recent order of use of the units is stored in a chronology array 15 and is updated, 16, in response to use of a unit, and if any units are eliminated from the system because of faults, the binary code is modified so that a first part identifies the eliminated unit and a second part indicates the most recent order of use of the remaining units. The invention is described generally as applied to a buffer 11 and address array 12 using a four-way set-associative technique in which each buffer section has a location for each page of a book of backing storage, a corresponding page of any book being placed in the appropriate page location in any section of buffer 11. The identity of the book from which a page comes is placed in the corresponding section of address array 12 at the same location within that section as the page location in buffer 11. A request on bus 10 interrogates all four sections of address array 12 and the book identities read out are compared at 13 with the requested book address to determine if the page is present in buffer 11. If the page is present, signals S1 to S4 indicate the buffer section in which the page is located and enable the appropriate read gate 14 to pass the accessed word from buffer 11. At the same time chronology array 15 is accessed at the appropriate page address and the usage code therein is updated at 16 and re-stored. If the page requested is not in buffer 11, a decode circuit 17 determines the least recently used (LRU) section for replacement. For a four-section buffer, the usage code is 6 bits indicating usage of section 1 before sections 2, 3, 4, section 2 before sections 3, 4, and section 3 before section 4. Certain code combinations are regarded as being invalid since they would result in "closed loop" interpretation of usage sequence. In the event of one or more sections of buffer 11 or address array 12 being withdrawn from service, a maintenance control (21, Fig. 2) forces a particular one of the "invalid" codes from a failure mode LRU decoder 22 instead of the normal code from the decoder (19). It is arranged that 3 bits of the "invalid" code represent the identity of the withdrawn sections and the other 3 bits of the code represent the order of use of the remaining sections. A further decoder (20) indicates error if the usage code is not among the set of normal and error mode codes. Details of the decoder circuits and different coding strategies are given.
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公开(公告)号：DE2610411A1
公开(公告)日：1976-10-07
申请号：DE2610411
申请日：1976-03-12
Applicant: IBM
Inventor： COOMBES DANIEL J , MESSINA BENEDICTO U
Abstract: 1484235 Memory paging; fault handling INTERNATIONAL BUSINESS MACHINES CORP 12 Feb 1976 [20 March 1975] 05513/76 Heading G4A In a storage system comprising a plurality of units, e.g. sections 1 to 4 of a high speed buffer 11, Fig. 1, which are used in a random sequence, a binary code reflecting the most recent order of use of the units is stored in a chronology array 15 and is updated, 16, in response to use of a unit, and if any units are eliminated from the system because of faults, the binary code is modified so that a first part identifies the eliminated unit and a second part indicates the most recent order of use of the remaining units. The invention is described generally as applied to a buffer 11 and address array 12 using a four-way set-associative technique in which each buffer section has a location for each page of a book of backing storage, a corresponding page of any book being placed in the appropriate page location in any section of buffer 11. The identity of the book from which a page comes is placed in the corresponding section of address array 12 at the same location within that section as the page location in buffer 11. A request on bus 10 interrogates all four sections of address array 12 and the book identities read out are compared at 13 with the requested book address to determine if the page is present in buffer 11. If the page is present, signals S1 to S4 indicate the buffer section in which the page is located and enable the appropriate read gate 14 to pass the accessed word from buffer 11. At the same time chronology array 15 is accessed at the appropriate page address and the usage code therein is updated at 16 and re-stored. If the page requested is not in buffer 11, a decode circuit 17 determines the least recently used (LRU) section for replacement. For a four-section buffer, the usage code is 6 bits indicating usage of section 1 before sections 2, 3, 4, section 2 before sections 3, 4, and section 3 before section 4. Certain code combinations are regarded as being invalid since they would result in "closed loop" interpretation of usage sequence. In the event of one or more sections of buffer 11 or address array 12 being withdrawn from service, a maintenance control (21, Fig. 2) forces a particular one of the "invalid" codes from a failure mode LRU decoder 22 instead of the normal code from the decoder (19). It is arranged that 3 bits of the "invalid" code represent the identity of the withdrawn sections and the other 3 bits of the code represent the order of use of the remaining sections. A further decoder (20) indicates error if the usage code is not among the set of normal and error mode codes. Details of the decoder circuits and different coding strategies are given.
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