公开(公告)号：JPS63116261A

公开(公告)日：1988-05-20

申请号：JP23275787

申请日：1987-09-18

Applicant: IBM

Inventor： COSTES MICHEL L ,  GACH ALAIN R ,  DUGRE JEAN-PIERRE C

IPC: G06F13/37

公开(公告)号：CA1273122A

公开(公告)日：1990-08-21

申请号：CA535923

申请日：1987-04-29

Applicant: IBM

Inventor： COSTES MICHEL L ,  DALBOUSSIERE GERARD ,  BARKER KENNETH

IPC: G06F13/00 ,  G06F13/12 ,  H04L69/14 ,  G06F9/22 ,  G06F9/28

Abstract: The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.

公开(公告)号：CA1241776A

公开(公告)日：1988-09-06

申请号：CA479573

申请日：1985-04-19

Applicant: IBM

Inventor： MONTANARI GERARD M ,  BAUDELOT FRANCIS E ,  COSTES MICHEL L

IPC: H04L1/00 ,  H04J3/14 ,  H04L69/40

Abstract: In a data communication system, a device for performing a wrap test on at least one line without affecting the other lines that transmit and receive data over at least one multiplex link within time slots allocated to a given line within a given frame. During each time slot, a wrap control bit is set by the communication system to a state that indicates either the wrap test mode or the normal mode of operations. Said bit controls a logic circuit to cause data to be sent either over link or to the receive circuit to perform the test, within each time slot.

公开(公告)号：FR2394217A1

公开(公告)日：1979-01-05

申请号：FR7813286

申请日：1978-04-27

Applicant: IBM

Inventor： COSTES MICHEL L ,  HOYLE JAMES F

IPC: H04M11/06 ,  G01R31/28 ,  H04B3/46 ,  H04B17/00 ,  H04L69/40 ,  H04M3/26 ,  H04M11/00 ,  H04L27/00

Abstract: The test circuit disconnects the active elements of the coupler from the input and output and applies a test signal to the input of the active elements. The output of the active elements is first compared with a first threshold which if exceeded or equaled provides a first indication. Within a predetermined time period the output of the active elements is compared with a second threshold to determine if the control function of the active element has reduced the input to the second threshold within the time period. If this condition prevails, the indication previously provided is removed; otherwise, the indication remains and a faulty coupler is indicated.

公开(公告)号：CA1088234A

公开(公告)日：1980-10-21

申请号：CA299815

申请日：1978-03-28

Applicant: IBM

Inventor： COSTES MICHEL L ,  HOYLE JAMES F

IPC: H04M11/06 ,  G01R31/28 ,  H04B3/46 ,  H04B17/00 ,  H04L69/40 ,  H04M3/26 ,  H04M11/00

Abstract: TEST CIRCUIT FOR A PROTECTIVE COUPLER The test circuit disconnects the active elements of the coupler from the input and output and applies a test signal to the input of the active elements. The output of the active elements is first compared with a first threshold which if exceeded or equaled provides a first indication. Within a predetermined time period the output of the active elements is compared with a second threshold to determine if the control function of the active element has reduced the input to the second threshold within the time period. If this condition prevails, the indication previously provided is removed; otherwise, the indication remains and a faulty coupler is indicated.

公开(公告)号：DE3685114D1

公开(公告)日：1992-06-04

申请号：DE3685114

申请日：1986-10-30

Applicant: IBM

Inventor： COSTES MICHEL L ,  GACH ALAIN R ,  DUGRE JEAN-PIERRE C

IPC: G06F13/37 ,  G06F13/36

Abstract: The priority enhancement circuit has adaptor selecting devices (17,27) to monitor the service requests from various different adapters and to prevent any adapter from raising a new service request whilst the other adapters have requests pending. The grant signal transmitted by an adapter number (n-1) is propagated on the chain directly to a first adapter number (n) on the one hand and to a second adapter number (H + 1), in which case the first adapter is by-passed by the grant signal. A selector device responds to a status signal indicating adapter to determine which of the contending grant signals has to be selected. If the status signal indicates that a given adapter is inoperative it is by-passed.