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    SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES
    1.
    发明申请
    SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES 审中-公开
    用于通信处理器和外部设备之间的指令和数据的系统和方法

    公开(公告)号：WO2007020274A3

    公开(公告)日：2007-04-19

    申请号：PCT/EP2006065372

    申请日：2006-08-16

    Applicant: IBM ,  IBM UK ,  DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

    IPC: G06F13/28 ,  G06F15/163 ,  H04Q3/545

    CPC classification number: G06F13/28

    Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

    Abstract translation: 提供了一种用于在处理器和外部设备之间传送指令和数据的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或者没有可用空间来写入对应的寄存器时，处理器处于低功率“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

    Direct deposit using locking cache
    3.
    发明专利
    Direct deposit using locking cache 有权
    使用锁定缓存的直接存款

    公开(公告)号：JP2006134324A

    公开(公告)日：2006-05-25

    申请号：JP2005313388

    申请日：2005-10-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES ,  TRUONG THUONG

    IPC: G06F12/08 ,  G06F12/12 ,  G06F13/12

    CPC classification number: G06F12/0848 ,  G06F12/0875

    Abstract: PROBLEM TO BE SOLVED: To store data into a portion of a cache or other fast memory without also writing it to main memory. SOLUTION: A method of storing data transferred from an I/O device, a network, or a disk into a portion of the cache or other fast memory, without also writing it to the main memory is provided. Further, the data is "locked" into the cache or other fast memory until it is loaded for use. The data remains in a locking cache until it is specifically overwritten under software control. In this embodiment, a processor can write data to the cache or other fast memory without writing it also to the main memory. The portion of the cache or other fast memory can be used as additional system memory. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：将数据存储到高速缓存或其他快速存储器的一部分中，而不将其写入主存储器。 提供了一种将从I / O设备，网络或磁盘传送的数据存储到高速缓存或其他快速存储器的一部分中的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到在软件控制下被特别覆盖。 在本实施例中，处理器可以将数据写入高速缓存或其他快速存储器，而不将其写入主存储器。 高速缓存或其他快速存储器的部分可以用作额外的系统存储器。 版权所有（C）2006，JPO＆NCIPI

    SYSTEM AND METHOD FOR LIMITING THE SIZE OF A LOCAL STORAGE OF A PROCESSOR
    5.
    发明申请
    SYSTEM AND METHOD FOR LIMITING THE SIZE OF A LOCAL STORAGE OF A PROCESSOR 审中-公开
    用于限制处理器的本地存储器大小的系统和方法

    公开(公告)号：WO2007020264B1

    公开(公告)日：2007-10-11

    申请号：PCT/EP2006065326

    申请日：2006-08-15

    Applicant: IBM ,  IBM UK ,  BURNS ADAM PATRICK ,  DAY MICHAEL NORMAN ,  FLACHS BRIAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL

    Inventor： BURNS ADAM PATRICK ,  DAY MICHAEL NORMAN ,  FLACHS BRIAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL

    IPC: G06F12/06

    CPC classification number: G06F12/0661 ,  G06F12/0223

    Abstract: A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

    Abstract translation: 提供了用于限制处理器的本地存储器的大小的系统和方法。 提供与处理器相关联的设施以设置本地存储大小限制。 该设施是一个特权设施，只能通过在多处理器系统中的控制处理器上运行的操作系统或相关处理器本身访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模是 用于访问本地存储。

    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS
    6.
    发明申请
    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS 审中-公开
    改进TLB管理实时应用程序

    公开(公告)号：WO2004053698A3

    公开(公告)日：2006-01-12

    申请号：PCT/GB0305108

    申请日：2003-11-21

    Applicant: IBM ,  IBM UK

    Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F12/126

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

    Abstract translation: 计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。 这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE
    7.
    发明申请
    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE 审中-公开
    在无序的DMA命令队列中建立命令顺序

    公开(公告)号：WO2006006084A3

    公开(公告)日：2006-07-20

    申请号：PCT/IB2005003169

    申请日：2005-07-06

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    Abstract translation: 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元在许多总线体系结构中已经司空见惯。 但是，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的大量命令并保留依赖关系，可以使用命令中的嵌入标志或屏障命令。 这些操作可以控制执行命令的顺序，从而保持依赖关系。

    System, method, computer program and device for communicating command parameter between processor and memory flow controller
    9.
    发明专利
    System, method, computer program and device for communicating command parameter between processor and memory flow controller 有权
    系统，方法，计算机程序和用于在处理器和存储器流量控制器之间通信命令参数的设备

    公开(公告)号：JP2007052790A

    公开(公告)日：2007-03-01

    申请号：JP2006221861

    申请日：2006-08-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOHNS CHARLES RAY ,  SWANSON TODD ,  LIU PEICHUN PETER ,  DAY MICHAEL NORMAN ,  TRUONG THUONG QUANG

    IPC: G06F15/80

    CPC classification number: G06F13/32 ,  G06F13/1642

    Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for communicating command parameters between a processor and a memory flow controller. SOLUTION: This application utilizes a channel interface as a main mechanism for communication between the processor and the memory flow controller. The channel interface provides a channel for executing communication with, for instance, a processor facility, a memory flow control facility, a machine status register, and an external processor interrupt facility. When data to be read from a corresponding register by a blocking channel are not usable or there is no writing space in the corresponding register, the processor is brought into a low-power "stall" state. When the data are made usable or a space is released, the processor is automatically called via communication on the blocking channel. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 解决方案：本应用程序利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口提供用于执行与例如处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备的通信的通道。 当通过阻塞通道从对应的寄存器读取的数据不可用或在对应的寄存器中没有写入空间时，处理器进入低功率“失速”状态。 当数据可用或释放空间时，通过阻塞通道上的通信自动调用处理器。 版权所有（C）2007，JPO＆INPIT

    System and method for loading software on multiple processors
    10.
    发明专利
    System and method for loading software on multiple processors 有权
    用于在多个处理器上加载软件的系统和方法

    公开(公告)号：JP2005100405A

    公开(公告)日：2005-04-14

    申请号：JP2004276674

    申请日：2004-09-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： AGUILAR MAXIMINO JR ,  CHENEN CHOU ,  DAY MICHAEL NORMAN ,  GOWEN MICHAEL STAN ,  MARK RICHARD NATTER ,  XENIDIS JAMES

    IPC: G06F9/54 ,  G06F9/445

    CPC classification number: G06F9/44557 ,  G06F9/44526

    Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for loading software on a plurality of processors. SOLUTION: A processing unit (PU) retrieves a file from a system memory and loads the file on the internal memory of the processing unit. The PU extracts a processor type from the header of the file. It is distinguished whether the file should be executed in, the PU or a synergistic processing unit (SPU) depending on its processor type. When the file should be executed in the SPU, the PU DMA (Direct Memory Access)-transfers the file to the SPU for execution. In one embodiment, the file is a combined file including both of a PU code and an SPU code. In the embodiment, the PU identifies one section header or a plurality of section headers included in the file. The section header(s) indicates the SPU code incorporated into the combined file. In the embodiment, the PU extracts the SPU code from the combined file and DMA-transfers the extracted code to the SPU for execution. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于在多个处理器上加载软件的系统和方法。 解决方案：处理单元（PU）从系统存储器检索文件，并将文件加载到处理单元的内部存储器上。 PU从文件的标题中提取处理器类型。 根据其处理器类型，区分是否应该执行文件，PU或协同处理单元（SPU）。 当文件应在SPU中执行时，PU DMA（直接内存访问） - 将文件传输到SPU执行。 在一个实施例中，该文件是包括PU代码和SPU代码两者的组合文件。 在本实施例中，PU识别文件中包括的一个部分标题或多个部分标题。 段标题表示并入组合文件中的SPU代码。 在本实施例中，PU从组合文件中提取SPU代码，DMA将提取的代码传送到SPU执行。 版权所有（C）2005，JPO＆NCIPI

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