公开(公告)号：US3756862A

公开(公告)日：1973-09-04

申请号：US3756862D

申请日：1971-12-21

Applicant: IBM

Inventor： AHN J ,  DE WITT D ,  JOHNSON W ,  KLEINFELDER W

IPC: H01L23/52 ,  H01J37/317 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/00 ,  H01L27/06 ,  H01L29/73 ,  H01L7/54

CPC classification number: H01L27/0658 ,  H01J37/3171 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/128 ,  Y10S148/145 ,  Y10S438/912

Abstract: IMPROVED SEMICONDUCTOR DEVICES ARE MADE BY THE METHOD OF PROTON ENHANCED DIFFUSION. A SEMICONDUCTOR WAFER HAVING A BURIED SUBCOLLECTOR REGION, IS RAISED TO AN ELEVATED TEMPERATURE AND EXPOSED TO AN ACCELERATED BEAM OF HYDROGEN OR HELIUM IONS WHICH MAY EITHER BE FOCUSED OR BE DIRECTED THROUGH A MASK. THE BEAM IS RENDERED INCIDENT ON THE SUBCOLLECTOR REGION. THE IONS PENETRATING THE SUBCOLLECTOR REGION ENHANCE THE DIFFUSION OF SUBCOLLECTOR TYPE IMPURITIES PRODUCING A COLLECTOR PEDESTAL AND A COLLECTOR REACH-THROUGH FOR A PEDESTAL TRANSISTOR. THE TRANSISTOR PRODUCED THEREBY HAS A UNIFORMLY NARROW BASE WIDTH HAVING A RELATIVELY LONG MINORITYU CARRIER LIFETIME AND VERY STEEP IMPURITY PROFILES. AN IMPROVED DIFFUSION CAPACITOR, IGFET, AND SUBSURFACE DIFFUSES INTERCONNECTION IS ALSO MADE BY THE METHOD OF PROTON ENHANCED DIFFUSION.

公开(公告)号：US3709746A

公开(公告)日：1973-01-09

申请号：US3709746D

申请日：1969-11-10

Applicant: IBM

Inventor： DE WITT D

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L27/00 ,  H01L7/36 ,  H01L19/00

CPC classification number: H01L21/743 ,  H01L27/00

Abstract: A DOUBLE EPITAXIAL PROCESS FOR FORMING A PEDESTAL TRANSISTOR COMPRISING THE STEPS OF PROVIDING A SUBSTRATE OF A FIRST CONDUCTIVITY TYPE AND THEN FORMING FIRST AND SECOND OPPOSITE CONDUCTIVELY TYPE EPTAXIAL LAYERS THEREOVER. DURING THE GROWTH OF THE EPITAXIAL LAYERS, SELECTED OUT-DIFFUSIONS FROM THE EPITAXIAL LAYERS FROM A BURIED SUBCOLLECTOR AND PEDESTAL COLLECTOR REGION. DIFFUSED ISOLATION REGIONS AND BASE AND EMITTER REGIONS ARE FORMED

TO COMPLETE THE DEVICE IN MONOLITHIC FORM. PRECISE THICKNESS AND CONCENTRATION CONTROL IN THE TOP EPITAXIAL LAYER AFFORDS OPTIMIZATION OR EXTRINSIC BASE-COLLECTOR CAPACITANCE.

公开(公告)号：SE325644B

公开(公告)日：1970-07-06

申请号：SE87967

申请日：1967-01-20

Applicant: IBM

Inventor： KARAN C ,  TOTTA P ,  DE WITT D ,  NAPIER J ,  SOPHER R

IPC: H01L1/14

公开(公告)号：CA931278A

公开(公告)日：1973-07-31

申请号：CA59710

申请日：1969-08-18

Applicant: IBM

Inventor： PLATT A ,  GATES H ,  DE WITT D

IPC: H01L21/761 ,  H01L29/08

Abstract: 1,263,127. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 19 Aug., 1969 [5 Sept., 1968], No. 41319/69. Heading H1K. An individual isolation wall surrounding each component in an I.C. is produced by diffusing a first region of the opposite conductivity type into a substrate, depositing a first epitaxial layer of the same conductivity type as the substrate, diffusing a frame region of the opposite conductivity type through the layer to contact the first region, depositing a second epitaxial layer, and diffusing a second frame region through this layer to contact the first frame region. An N--type Si wafer (10) is thermally oxidized and the oxide photolithographically processed to provide openings into which an impurity is diffused to form P-type isolation regions (12), Fig. 2a (not shown). The surface is reoxidized and all the oxide removed and an N--type epitaxial layer (16) is deposited by the hydrogen reduction of SiCl 4 , Fig. 2b (not shown). The surface is oxide masked and impurities are diffused-in to form an annular P-type region (18), Fig. 2c (not shown), and an N + -type subcollector region 20, Fig. 2d (not shown). A second N--type epitaxial layer 22 is then deposited and a P-type annular region 28, and N + -type collector contact region 24, a P-type base region 26 and an N + -type emitter region 32 are formed by diffusion. During subsequent epitaxial growth and diffusion steps the impurities in P-type regions 12 and 18 and in N-type region 20 diffuse into the overlying layers so that the transistor is completely surrounded by a P-type isolation region and the region 24 contacts the sub-collector region 20. The N + -type collector contact region 24 and the emitter region 32 may be doped with phosphorus. The base region 26 may be formed simultaneously with the P-type isolation region 28. A low resistance cross-over may be provided in the wafer by forming a P-type "column" simultaneously with the three isolation region diffusions, conductive tracks in one direction passing over the "column" on an insulating layer while a track extending at right angles to the first direction is broken and has its ends in contact with spaced parts of the top of the "column" which completes the circuits, Fig. 3 (not shown).

公开(公告)号：SE334423B

公开(公告)日：1971-04-26

申请号：SE1472467

申请日：1967-10-27

Applicant: IBM

Inventor： CASTUCCI P ,  DE WITT D ,  DHAKA V ,  MUTTER W

IPC: H01L21/00 ,  H01L21/331 ,  H01L23/485 ,  H01L29/00 ,  H01L1/14

Abstract: 1,174,832. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1967 [27 Oct., 1966], No. 44711/67. Heading H1K. [Also in Division C7] A method of forming an elongated metal contact on a semi-conductor device comprises; (a) providing a protective coating, preferably of silicon dioxide or silicon nitride, on the semiconductor surface and forming at least one elongated aperture in the coating; (b) depositing a first layer of metal, preferably Pt, Pd or Mo, over the protective coating and the exposed semi-conductor surface to form an ohmic contact with the semi-conductor; (c) removing the metal from the protective coating; (d) depositing, e.g. by electroplating or by chemical or electroless deposition, a second layer of metal, preferably palladium, over the first layer within the aperture to increase the conductivity of the contact; and (e) depositing a third layer of metal over the protective coating to form an external hand pattern having an extension overlaying a portion only of the second layer. The third layer may consist of Al, Mo or a sandwich of Cu-Mo, Cr-Cu, Mo-Cu or Mo-Au.