公开(公告)号：WO2005017976A3

公开(公告)日：2005-04-28

申请号：PCT/EP2004051772

申请日：2004-08-11

Applicant: IBM ,  IBM UK ,  DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/76256 ,  H01L21/76275 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: The present invention provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafers, wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

Abstract translation: 本发明提供SOI CMOS技术，其中使用多晶硅背栅来控制前栅器件的阈值电压，并且nMOS和pMOS背栅相互独立地切换并且前栅极被切换。 具体而言，本发明提供了一种制造背栅全耗尽CMOS器件的方法，其中器件的背栅与器件的前栅以及源/漏延伸部自对准。 这样的结构使电容最小化，同时增强了器件和电路性能。 使用现有的SIMOX（通过氧离子注入分离）或键合SOI晶片，晶片键合和减薄，多晶Si刻蚀，低压化学气相沉积和化学机械抛光来制造本发明的背栅全耗尽CMOS器件。

公开(公告)号：DE602004003967T2

公开(公告)日：2007-08-30

申请号：DE602004003967

申请日：2004-08-11

Applicant: IBM

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

公开(公告)号：DE602004003967D1

公开(公告)日：2007-02-08

申请号：DE602004003967

申请日：2004-08-11

Applicant: IBM

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

公开(公告)号：AT349773T

公开(公告)日：2007-01-15

申请号：AT04766475

申请日：2004-08-11

Applicant: IBM

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L21/00

Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.