公开(公告)号：FR2425125A1

公开(公告)日：1979-11-30

申请号：FR7909109

申请日：1979-04-04

Applicant: IBM

Inventor： DEUTSCH ALINA N ,  KRYDER MARK H ,  NYSTROM WALTER N

IPC: G11C11/14 ,  G11C19/08 ,  G11C19/28

Abstract: A magnetic bubble domain storage system comprising an array of rows and columns of logical chips are organized into logical half-chips with even numbered bits in one half-chip and odd numbered bits in the other half-chip. Alternating rows of half-chips are used for storing even numbered bits and odd numbered bits, respectively. Each half-chip has its own bubble domain generator, but a common generator current line serves all generators for a row of even half-chips and all generators for a row of odd half-chips. Thus, information is written into even half-chips and odd half-chips at the same time by pulsing the generator current line common to a row of even half-chips and a row of odd half-chips. Each half-chip has a sensing element and all the sensing elements corresponding to a row of half-chips are connected in series. The series connection of sensors in any row forms one leg of a bridge circuit, and another leg of the bridge circuit is another series connection of sensors in another row of the storage array. One of these legs corresponds to sensors from a row of even half-chips while the other leg corresponds to sensors from a row of odd half-chips. The other two legs of the bridge circuit are comprised of dummy resistors. Even though two rows of sensors are connected to the same bridge circuit, even numbered bits and odd numbered bits will be read at alternating times.