公开(公告)号：GB2590888B

公开(公告)日：2021-10-27

申请号：GB202106472

申请日：2019-09-25

Applicant: IBM

Inventor： JOHN VERNON` ARTHUR ,  ANDREW STEPHEN CASSIDY ,  MYRON FLICKNER ,  PALLAB DATTA ,  HARTMUT PENNER ,  RATHINAKUMAR APPUSWAMY ,  JUN SAWADA ,  DHARMENDRA MODHA ,  STEVEN KYLE ESSER ,  BRIAN SEISHO TABA ,  JENNIFER KLAMO

IPC: G06N3/063 ,  G06N3/02

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

公开(公告)号：GB2590888A

公开(公告)日：2021-07-07

申请号：GB202106472

申请日：2019-09-25

Applicant: IBM

Inventor： JOHN VERNON` ARTHUR ,  ANDREW STEPHEN CASSIDY ,  MYRON FLICKNER ,  PALLAB DATTA ,  HARTMUT PENNER ,  RATHINAKUMAR APPUSWAMY ,  JUN SAWADA ,  DHARMENDRA MODHA ,  STEVEN KYLE ESSER ,  BRIAN SEISHO TABA ,  JENNIFER KLAMO

IPC: G06N3/063 ,  G06N3/02

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to:receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores,output of one or more neural network layers.