公开(公告)号：CA1106975A

公开(公告)日：1981-08-11

申请号：CA285875

申请日：1977-08-31

Applicant: IBM

Inventor： ARNOLD RICHARD F ,  DISHON YITZHAK ,  OUCHI NORMAN K ,  SCHOR MARSHALL I

IPC: H03M7/40 ,  H03M7/42 ,  H04L23/00 ,  G06F13/06

Abstract: A MARKOV PROCESSOR FOR CONTEXT ENCODING FROM GIVEN CHARACTERS AND FOR CHARACTER DECODING FROM GIVEN CONTEXTS In an apparatus for generating variable length codewords c(ai) and c(aj) responsive to corresponding fixed length codewords b(ai) and b(aj), where ai and aj are source alphabet characters, ai.epsilon.A1 and aj.epsilon.A2,ambiguity arises whenever any fixed length charac-ter to be encoded can instantaneously represent source characters ai and aj drawn from two or more dissimilar alphabets i.e., A1 or A2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths. This map models certain statistical regularities of runs of fixed code elements and the relative likelihood that an ambiguous fixed code character appearing in a first run belongs to a given alphabet. The processor, starting from an arbitrary initial position, tracks any given run of fixed code characters applied to the encoder in terms of a succession of states and paths. SA9-75-024 -1-

公开(公告)号：FR2363830A1

公开(公告)日：1978-03-31

申请号：FR7724680

申请日：1977-08-01

Applicant: IBM

Inventor： ARNOLD RICHARD F ,  DISHON YITZHAK ,  OUCHI NORMAN K ,  SCHOR MARSHALL I

IPC: H03M7/40 ,  H03M7/42 ,  H04L23/00 ,  G06F5/00 ,  H03K13/24

Abstract: In an apparatus for generating variable length codewords c(ai) and c(aj) responsive to corresponding fixed length codewords b(ai) and b(aj), where ai and aj are source alphabet characters, ai epsilon A1 and aj epsilon A2, ambiguity arises whenever any fixed length character to be encoded can instantaneously represent source characters ai and aj drawn from two or more dissimilar alphabets i.e. A1 or A2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths. This map models certain statistical regularities of runs of fixed code elements and the relative likelihood that an ambiguous fixed code character appearing in a first run belongs to a given alphabet. The processor, starting from an arbitrary initial position, tracks any given run of fixed code characters applied to the encoder in terms of a succession of states and paths.

公开(公告)号：DE3751448T2

公开(公告)日：1996-05-02

申请号：DE3751448

申请日：1987-11-06

Applicant: IBM

Inventor： DISHON YITZHAK ,  KIM MICHELLE YOONKYUNG-LEE

IPC: G06F13/10 ,  G06F3/06 ,  G06F11/20 ,  G11B19/28 ,  G11B21/08 ,  G11C29/00 ,  G11B5/596

Abstract: At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronized with each other except during the power up phase. The DASD synchronization is controlled and maintained by synchronization control means independent of any commands from the CPU. When one or more commands such as SEEK and SET SECTOR or LOCATE commands are transferred from the CPU to a control unit over a single data transfer path between them, desired identical records on the synchronized DASDs are concurrently located while the DASDs are disconnected from the data transfer path. Upon locating the desired identical records, the DASDs are reconnected to the data transfer path. Then, a WRITE command is transferred from the CPU to the control unit for concurrently recording the same data onto the synchronized DASDs at the desired record locations. Thus, at the conclusion of this recording, when status information is reported to the host CPU, it is assured that multiple copies of the same data are recorded onto the synchronized DASDs.

公开(公告)号：AU2814177A

公开(公告)日：1979-03-08

申请号：AU2814177

申请日：1977-08-23

Applicant: IBM

Inventor： ARNOLD RICHARD FAIRBANKS ,  DISHON YITZHAK ,  OUCHI NORMAN KEN ,  SCHOR MARSHALL I

IPC: H03M7/40 ,  H03M7/42 ,  H04L23/00 ,  H04L3/00 ,  G06F15/38 ,  H03K13/24

Abstract: In an apparatus for generating variable length codewords c(ai) and c(aj) responsive to corresponding fixed length codewords b(ai) and b(aj), where ai and aj are source alphabet characters, ai epsilon A1 and aj epsilon A2, ambiguity arises whenever any fixed length character to be encoded can instantaneously represent source characters ai and aj drawn from two or more dissimilar alphabets i.e. A1 or A2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths. This map models certain statistical regularities of runs of fixed code elements and the relative likelihood that an ambiguous fixed code character appearing in a first run belongs to a given alphabet. The processor, starting from an arbitrary initial position, tracks any given run of fixed code characters applied to the encoder in terms of a succession of states and paths.

公开(公告)号：DE3751448D1

公开(公告)日：1995-09-14

申请号：DE3751448

申请日：1987-11-06

Applicant: IBM

Inventor： DISHON YITZHAK ,  KIM MICHELLE YOONKYUNG-LEE

IPC: G06F13/10 ,  G06F3/06 ,  G06F11/20 ,  G11B19/28 ,  G11B21/08 ,  G11C29/00 ,  G11B5/596

Abstract: At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronized with each other except during the power up phase. The DASD synchronization is controlled and maintained by synchronization control means independent of any commands from the CPU. When one or more commands such as SEEK and SET SECTOR or LOCATE commands are transferred from the CPU to a control unit over a single data transfer path between them, desired identical records on the synchronized DASDs are concurrently located while the DASDs are disconnected from the data transfer path. Upon locating the desired identical records, the DASDs are reconnected to the data transfer path. Then, a WRITE command is transferred from the CPU to the control unit for concurrently recording the same data onto the synchronized DASDs at the desired record locations. Thus, at the conclusion of this recording, when status information is reported to the host CPU, it is assured that multiple copies of the same data are recorded onto the synchronized DASDs.

公开(公告)号：CA1105141A

公开(公告)日：1981-07-14

申请号：CA359579

申请日：1980-09-04

Applicant: IBM

Inventor： ARNOLD RICHARD F ,  DISHON YITZHAK ,  OUCHI NORMAN K ,  SCHOR MARSHALL I

IPC: H03K9/08 ,  H03K13/01

Abstract: A MARKOV PROCESSOR FOR CONTEXT ENCODING FROM GIVEN CHARACTERS AND FOR CHARACTER DECODING FROM GIVEN CONTEXTS In an apparatus for generating variable length codewords c(aj) and c(aj) responsive to corresponding fixed length codewords b(ai) and b(aj), where ai and aj are source alphabet characters, ai.epsilon.Al and aj.epsilon.A2, ambiguity arises whenever any fixed length charac-ter to be encoded can instantaneously represent source characters aj and aj drawn from two or more dissimilar alphabets i.e., A1 or A2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths. This map models certain statistical regularities of runs of fixed code elements and the relative likelihood that an ambiguous fixed code character appearing in a first run belongs to a given alphabet. The processor, starting from an arbitrary initial position, tracks any given run of fixed code characters applied to the encoder in terms of a succession of states and paths. SA9-75-024

公开(公告)号：DE2735319A1

公开(公告)日：1978-03-09

申请号：DE2735319

申请日：1977-08-05

Applicant: IBM

Inventor： ARNOLD RICHARD FAIRBANKS ,  DISHON YITZHAK ,  OUCHI NORMAN KEN ,  SCHOR MARSHALL I

IPC: H03M7/40 ,  H03M7/42 ,  H04L23/00 ,  G06F5/00

Abstract: In an apparatus for generating variable length codewords c(ai) and c(aj) responsive to corresponding fixed length codewords b(ai) and b(aj), where ai and aj are source alphabet characters, ai epsilon A1 and aj epsilon A2, ambiguity arises whenever any fixed length character to be encoded can instantaneously represent source characters ai and aj drawn from two or more dissimilar alphabets i.e. A1 or A2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths. This map models certain statistical regularities of runs of fixed code elements and the relative likelihood that an ambiguous fixed code character appearing in a first run belongs to a given alphabet. The processor, starting from an arbitrary initial position, tracks any given run of fixed code characters applied to the encoder in terms of a succession of states and paths.