公开(公告)号：JP2007179528A

公开(公告)日：2007-07-12

申请号：JP2006273480

申请日：2006-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOMBROWSKI CHRIS ,  NGAN NGOC PHAM ,  KORNEGAY MARCUS L

IPC: G06F12/08

CPC classification number: G06F12/0833

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for default data forwarding coherent caching agent.
SOLUTION: A node controller receives a cache line request from either a local caching agent (local processor) or from a remote node controller. When the node controller receives a request from a local caching agent, the node controller sends the corresponding cache line to the local caching agent, all the while maintaining cache line forward state control. When the node controller receives a request from a remote node controller, the node controller sends the cache line, along with the cache line forward state control, to the remote node controller. In addition, the node controller performs particular actions based upon the source of the cache line request, the request type, and the cache line current status.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于默认数据转发相干缓存代理的系统和方法。 解决方案：节点控制器从本地缓存代理（本地处理器）或远程节点控制器接收高速缓存行请求。 当节点控制器从本地缓存代理接收请求时，节点控制器将相应的缓存行发送到本地缓存代理，同时保持高速缓存行向前状态控制。 当节点控制器从远程节点控制器接收到请求时，节点控制器将高速缓存行与高速缓存行前向状态控制一起发送到远程节点控制器。 此外，节点控制器基于高速缓存行请求的来源，请求类型和高速缓存行当前状态来执行特定动作。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007183915A

公开(公告)日：2007-07-19

申请号：JP2006273451

申请日：2006-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOMBROWSKI CHRIS ,  PHAM NGAN N ,  KORNEGAY MARCUS L

IPC: G06F12/08

CPC classification number: G06F12/0817

Abstract: PROBLEM TO BE SOLVED: To provide a system for maintaining data consistency in a multiprocessor system.
SOLUTION: A first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to a second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在多处理器系统中维持数据一致性的系统。 解决方案：第一处理器被配置为确定在第一处理器的高速缓存中是否没有找到数据线，并将数据线的请求转发到第二处理器。 第二处理器被配置为将数据线从第二处理器转发到第一处理器，更新第二处理器的目录以反映被转发到第一处理器的数据线，并将目录更新消息转发到至少一个附加处理器 以反映被转发到第一处理器的数据线。 目录中的条目包括存储器地址，最近的数据保持器和线路状态。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA2074633A1

公开(公告)日：1993-03-04

申请号：CA2074633

申请日：1992-07-24

Applicant: IBM

Inventor： BAKER ROBERT G ,  DEBAUCHE BRADLEY J ,  DOMBROWSKI CHRIS ,  JENSEN ERIC ,  MASSMAN LLOYD H ,  MCCAIN MELVIN ,  SWINGLE PAUL R

IPC: G06F15/16 ,  G06F9/48 ,  G06F9/38 ,  G06F13/12

公开(公告)号：CA2074633C

公开(公告)日：1998-03-31

申请号：CA2074633

申请日：1992-07-24

Applicant: IBM

Inventor： MASSMAN LLOYD H ,  DEBAUCHE BRADLEY J ,  SWINGLE PAUL R ,  DOMBROWSKI CHRIS ,  JENSEN ERIC ,  BAKER ROBERT G ,  MCCAIN MELVIN

IPC: G06F15/16 ,  G06F9/48 ,  G06F9/38 ,  G06F13/12

Abstract: A personal computer system includes a digital signal processor (DSP) subsystem that is connectable to a plurality of application specific hardware devices. A single DSP is operable under a DSP real-time operating system (RTOS) to concurrently handle a plurality of different signal processing functions on a real-time basis. A DSP data store is connected to the DSP and to the personal computer and includes addressable locations that emulate addressable I/O registers associated with the application specific hardware devices to enable the personal computer to run a plurality of application programs controlling operation of the hardware devices. Performance is enhanced for I/O read and write operations by delaying halting of the DSP allowing such operations to complete in a cycle during which the DSP is not accessing the data store.

公开(公告)号：BR9203416A

公开(公告)日：1993-04-06

申请号：BR9203416

申请日：1992-09-01

Applicant: IBM

Inventor： BAKER ROBERT G ,  DEBAUCH BRADLEY J ,  DOMBROWSKI CHRIS ,  JENSEN ERIC ,  MASSMAN LLOYD H ,  MOCAIN MELVIN ,  SWINGLE PAUL RICHARD

IPC: G06F15/16 ,  G06F9/48 ,  G06F13/14