公开(公告)号：US3889243A

公开(公告)日：1975-06-10

申请号：US40768873

申请日：1973-10-18

Applicant: IBM

Inventor： DRIMAK EDWARD G

IPC: G11C7/00 ,  G06F9/34 ,  G06F9/40 ,  G06F12/08 ,  G06F13/00

CPC classification number: G06F9/4425 ,  G06F12/08 ,  G06F2212/451

Abstract: A storage device (hereinafter referred to as a high speed store) includes a plurality of registers or locations and has an access speed compatible with that of its processor. Operand and operator entries are entered into one group of said registers in descending and ascending order from opposite ends thereof (a push operation) and removed therefrom (a pop operation) for processing each entry type in a last-in-first-out order. The group of registers is hereinafter referred to as a high speed stack. The number of entries stored in the stack at any moment can become very large due to the nesting of operators. Since it is not economically feasible to provide a large capacity high speed stack, overflow of the stack into a slower speed storage device (hereinafter called a low speed stack) is provided. ''''Roll out'''' of entries to the low speed stack and ''''roll in'''' of the entries back to the high speed stack is effected as the high speed stack becomes full and empty. When a new entry is to be stored into the high speed stack (a push operation) and the stack is full after the entry is stored therein, the entries are rolled out from the high speed stack to the low speed stack. Pointers (stack addresses), together with their pointer registers, pointer updating circuits and pointer controlled logic, automatically select the stack registers as entries are pushed thereon and popped therefrom. When entries are rolled out, the pointers are rolled out with the entries and the pointer registers are reinitialized. When the entries are subsequently rolled in, their pointers are rolled in and set in the pointer registers. Hardware is provided for reserving some of the high speed stack registers for direct addressing by instructions rather than by the automatic pointer addressing mechanism.

Abstract translation: 存储装置（以下称为高速存储器）包括多个寄存器或位置，并具有与其处理器兼容的访问速度。 操作数和操作员条目以其从其相对端（推动操作）的降序和升序顺序输入到一组所述寄存器中，并从中移除（弹出操作），用于以先进先出顺序处理每个输入类型。 寄存器组以下称为高速堆栈。 由于操作员的嵌套，任何时刻存储在堆栈中的条目数可能变得非常大。 由于提供大容量的高速堆叠不是经济上可行的，所以提供了堆叠进入较慢速存储装置（以下称为低速堆叠）的溢流。 当高速堆栈变满并空时，将条目“转出”到低速堆栈，并将条目“滚入”回到高速堆栈。 当将新条目存储到高速堆栈（推送操作）中并且在存储条目之后堆栈已满时，条目从高速堆栈推出到低速堆栈。 指针（堆栈地址）与它们的指针寄存器，指针更新电路和指针控制逻辑一起，自动选择堆栈寄存器作为条目被推送并从中弹出。 当条目被推出时，指针将被输出并且指针寄存器被重新初始化。 当条目随后滚动时，它们的指针被滚动并设置在指针寄存器中。 提供了硬件来保留一些高速堆栈寄存器，用于通过指令而不是自动指针寻址机制进行直接寻址。

公开(公告)号：US3599176A

公开(公告)日：1971-08-10

申请号：US3599176D

申请日：1968-01-02

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  HUTCHINSON RICHARD J ,  SCHAUGHENCY MICHAEL F ,  SHIMP EVERETT M

IPC: G06F9/22 ,  G06F9/34 ,  G06F12/04 ,  G06F13/10 ,  G06F13/34 ,  G06F15/78 ,  G06F9/16

CPC classification number: G06F13/34 ,  G06F9/34 ,  G06F12/04 ,  G06F13/10 ,  G06F15/78

Abstract: A data processing system characterized by a high speed local storage unit used for storage of addresses and data involved in a variety of operations. Accesses to a main storage unit, containing both macroprogram and microprogram information, is under the control of addresses held in local storage. Transfer from a main line program to an interrupt subroutine is also handled by the local storage unit.

公开(公告)号：US3576544A

公开(公告)日：1971-04-27

申请号：US3576544D

申请日：1968-10-18

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  PERKINS CHARLES B JR

IPC: G06F12/14 ,  G06F11/10 ,  G08B29/00

CPC classification number: G06F12/1466

Abstract: A system for protecting data in storage against inadvertent alteration. An access to main storage is preceded by an access to auxiliary storage. A portion of the auxiliary storage address is used to address a local storage unit for a protection key. When main storage is accessed, a portion of the main storage address is used to address the local storage unit for a storage key relating to the addressed area in main storage. The keys are compared and alteration of data at the main storage address is prevented if the keys do not match.

公开(公告)号：FR2314536A1

公开(公告)日：1977-01-07

申请号：FR7610905

申请日：1976-04-08

Applicant: IBM

Inventor： DRIMAK EDWARD G ,  METZ THOMAS A

IPC: G06F12/06 ,  G06F12/02 ,  G06F12/04 ,  G06F9/20

Abstract: Two separate address lines are provided for each storage line of local storage. One address line is connected to a first group of bytes and the second address line is connected to the remaining bytes with each storage line containing the same addressing connection. Control circuits are provided for selecting any two address lines where the combination of the two provides access to both byte groups.

公开(公告)号：CA884025A

公开(公告)日：1971-10-19

申请号：CA884025D

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  HUTCHINSON RICHARD J ,  SCHAUGHENCY MICHAEL F ,  SHIMP EVERETT M

公开(公告)号：CA888407A

公开(公告)日：1971-12-14

申请号：CA888407D

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  PERKINS CHARLES B JR

公开(公告)号：CA884026A

公开(公告)日：1971-10-19

申请号：CA884026D

Applicant: IBM

Inventor： HUTCHINSON RICHARD J ,  SCHAUGHENCY MICHAEL F ,  SHIMP EVERETT M ,  CORDERO HUMBERTO JR ,  DRIMAK EDWARD G