-
公开(公告)号：US3626381A
公开(公告)日：1971-12-07
申请号：US3626381D
申请日：1969-10-20
Applicant: IBM
Inventor： DUBINSKY ALEXANDRE , TITMAN PETER J
CPC classification number: G06K9/68
Abstract: Graphical patterns, such as characters, are represented by sets of binary symmetric numbers (1, - 1). An associative store holds a first table of numbers (1, 0, - 1) organized into words representing the coefficients of hyperplanes for dividing a pattern space into volumes such that points in the same volume belong to the same pattern class. Each hyperplane representation is contained in a pair of words holding respectively the true and complemented forms of the hyperplane coefficients. A first associative table look-up determines which word of each pair more closely matches a particular pattern number set, by using the number set as a search argument. The resulting binary number string, indicative of a particular volume in the pattern space, is then used as a search argument for a second table in the store. The second table is organized into words representing each individual volume and the name of the pattern associated with that volume. An exact match on the second table look-up thus produces an output indicative of the name of the pattern to be recognized.
-
公开(公告)号：DE1953451A1
公开(公告)日：1970-06-04
申请号：DE1953451
申请日：1969-10-23
Applicant: IBM
Inventor： DUBINSKY ALEXANDRE , JAMES WINCHESTER TITMAN PETER
Abstract: 1,230,834. Character recognition; associative stores. INTERNATIONAL BUSINESS MACHINES CORP. 23 Oct., 1968, No. 50202/68. Headings G4C and G4R. A set of d binary symmetric (i.e. possible values + 1 and -1) numbers, e.g. from matrix optical sensing of a character to be recognized, is classified by using it to interrogate entries in an associative store representing the coefficients, restricted to possible values + 1, 0, -1, of the equations of planes in d-space which divide the space into volumes such that substantially all points in the same volume represent sets of numbers belonging to the same class, to obtain an indication of on which side of each plane the point representing the set of numbers to be classified lies, these indications being used to interrogate other entries in the same (or a different) associative store to identify the volume in which the point lies. The store holds two words for each plane, holding the coefficients in true and complement form respectively, the complements of + 1, 0, -1 being -1, 0, + 1 respectively, and + 1, -1, 0 being stored as 1, 0 and " don't care " respectively. " Don't care " gives a match whatever the interrogating input. Analogue voltages, one from each word, represent the extent of mismatch, and these two voltages for each plane are subtracted in a differential amplifier to set a latch or not according to the sign of the result to indicate on which side of the plane the point lies. Alternatively, interrogation for a given plane may be serial by word and bit each bit mismatch with one word incrementing a counter and each with the other decrementing it. The " which side of plane " bits, set into latches, are used to interrogate the second set of entries, each of which includes a set of such bits for a respective volume and a name associated with the volume which is read out to identify the character.
-
公开(公告)号：CA944081A
公开(公告)日：1974-03-19
申请号：CA63330
申请日：1969-09-29
Applicant: IBM
Inventor： DUBINSKY ALEXANDRE , TITMAN PETER J
IPC: G06K9/68
Abstract: 1,230,834. Character recognition; associative stores. INTERNATIONAL BUSINESS MACHINES CORP. 23 Oct., 1968, No. 50202/68. Headings G4C and G4R. A set of d binary symmetric (i.e. possible values + 1 and -1) numbers, e.g. from matrix optical sensing of a character to be recognized, is classified by using it to interrogate entries in an associative store representing the coefficients, restricted to possible values + 1, 0, -1, of the equations of planes in d-space which divide the space into volumes such that substantially all points in the same volume represent sets of numbers belonging to the same class, to obtain an indication of on which side of each plane the point representing the set of numbers to be classified lies, these indications being used to interrogate other entries in the same (or a different) associative store to identify the volume in which the point lies. The store holds two words for each plane, holding the coefficients in true and complement form respectively, the complements of + 1, 0, -1 being -1, 0, + 1 respectively, and + 1, -1, 0 being stored as 1, 0 and " don't care " respectively. " Don't care " gives a match whatever the interrogating input. Analogue voltages, one from each word, represent the extent of mismatch, and these two voltages for each plane are subtracted in a differential amplifier to set a latch or not according to the sign of the result to indicate on which side of the plane the point lies. Alternatively, interrogation for a given plane may be serial by word and bit each bit mismatch with one word incrementing a counter and each with the other decrementing it. The " which side of plane " bits, set into latches, are used to interrogate the second set of entries, each of which includes a set of such bits for a respective volume and a name associated with the volume which is read out to identify the character.
-
公开(公告)号：GB1275535A
公开(公告)日：1972-05-24
申请号：GB593171
申请日：1971-03-03
Applicant: IBM
Inventor： DUBINSKY ALEXANDRE
Abstract: 1275535 Digital computers INTERNATIONAL BUSINESS MACHINES CORP 3 March 1971 5931/71 Heading G4A A digital electric data processing arrangement in which two or more district processes may be performed concurrently comprises a plurality of serially reusable resources (i.e. units that can be used by only one process at a time) and means for identifying the sequence of use of the resources by means of graph theory. A scheduler receives data concerning the resources and sequencing of the processes and constructs a digital vector graph which indicates whether a complete vector circuit exists or not and this is displayed on a CRT or printed out. This is stated to prevent deadlock situations occurring i.e. where two processes are waiting for each other. The Apparatus.-This comprises a central processor having a microcode store, an arithmetic unit, several other stores and the scheduler. Connected thereto are a disc store, a multiplexer, and three channels connected respectively to a console or card reader/punch devices, a display unit, and disc stores. Two processes or more can be performed concurrently. Operation.-Four processes I-IV respectively use the following resources in these sequences: A, C ; A, B, C ; A, B, D, C ; C, B. In Fig. 5A each resource A to D is shown as a vertex of a graph and each process is shown as a path (i.e. a number of arcs between vertices). The scheduler has two stores FOSTACK and FLAGSTACK and the following algorithm is performed: 1. The vertices of the graph G without predecessors (i.e. A) are stored in FOSTACK. If FOSTACK is then empty step 4 is performed, if not step 2 is performed. 2. The top vertex from FOSTACK is deleted and all its successors (i.e. B, C) are stored in FLAGSTACK (Fig. 5C, not shown). 3. One vertex is taken from FLAGSTACK, checked for predecessors, and if it has none it is stored in FOSTACK. This is repeated until FLAGSTACK is empty. Both B and C have predecessors, G is unchanged, FOSTACK is empty hence there is a circuit. 4. If FOSTACK is empty and all vertices are deleted from G, there is no circuit. If there are vertices in G there is a circuit. If FOSTACK is not empty, step 1 is returned to. Figs. 5E and 6 (not shown) indicate how matrix theory can be used for the schedules to store the graph and another embodiment is described using this (Figs. 7 and 8, not shown). If a deadlock is found, the operator is shown the circuit on the CRT and can remedy it by, for example, delaying the operation.
-
-
-
Search Results
4
records
(took 0.036 seconds)
