公开(公告)号：EP0742512A3

公开(公告)日：1998-08-26

申请号：EP96106145

申请日：1996-04-19

Applicant: IBM

Inventor： EBICIOGLU MAHMUT ,  LUICK DAVID ARNOLD ,  MORENO JAIME HUMBERTO ,  SILBERMAN GABRIEL MAURICIO ,  WINTERFIELD PHILIP

IPC: G06F9/38

CPC classification number: G06F9/383 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3865

Abstract: A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.