公开(公告)号：CA1124134A

公开(公告)日：1982-05-25

申请号：CA365263

申请日：1980-11-21

Applicant: IBM

Inventor： BOLCAVAGE RICHARD D ,  FERRARO ARMAND J ,  FLEEK ARTHUR E

IPC: G06F3/12 ,  B41J1/20 ,  B41J5/30 ,  B41J7/36 ,  B41J29/38 ,  G06K15/07 ,  G06K15/08

Abstract: A belt printer control system for attachment to a host system has a first microprocessor connected by a dedicated bus to the host system and control elements operable to perform carriage control, belt drive, and ribbon drive operations of the printer mechanism. A second microprocessor is connected by a dedicated bus structure to controls for operating the print hammers. A common RAM is accessed by the two microprocessors through a common bus structure. The first microprocessor passes control and print information to the RAM for use by the second microprocessor in building print algorithm tables in the RAM for use by the second microprocessor to operate the print hammers. Communication between the microprocessors is done through control information stored by the microprocessors in the common RAM. Storing printing information and building of tables and controlling printing and nonprinting operations of the print mechanism are done concurrently. EN979014

公开(公告)号：AU539581B2

公开(公告)日：1984-10-04

申请号：AU7090881

申请日：1981-05-21

Applicant: IBM

Inventor： BOLCAVAGE RICHARD D ,  FERRARO ARMAND J ,  FLEEK ARTHUR E

IPC: G06K15/08 ,  G06F3/12 ,  G06K15/02

公开(公告)号：CA1159710A

公开(公告)日：1984-01-03

申请号：CA365265

申请日：1980-11-21

Applicant: IBM

Inventor： BOLCAVAGE RICHARD D ,  FERRARO ARMAND J ,  FLEEK ARTHUR E

IPC: B41J9/54 ,  B41J7/96 ,  B41J9/52 ,  G06F11/10 ,  G06K15/06 ,  G06K15/08 ,  B41J5/30

Abstract: A printer control system for a belt printer has an arrangement for checking print hammer operating circuits by comparing a real time actual parity of the circuits with a precalculated expected parity. Prior to printing, a microprocessor calculates expected parity bytes for each subscan for storage in a storage device along with the print position fire data used for selecting the operating circuits to be activated in the related subscans. An actual parity byte is generated on a real time basis by ODD/EVEN parity circuits associated with groups of operating circuits for comparison with a composite parity byte generated each subscan by the microprocessor. The composite parity byte is generated by combining the expected parity bytes from the storage device for several successive subscans. The composite parity byte is updated each subscan by a process of subtracting the initial expected parity byte and adding a new subscan expected parity byte. Comparison is made when all the activating circuits are in stable condition. EN979013

公开(公告)号：AU7090881A

公开(公告)日：1982-11-25

申请号：AU7090881

申请日：1981-05-21

Applicant: IBM

Inventor： BOLCAVAGE RICHARD D ,  FERRARO ARMAND J ,  FLEEK ARTHUR E

IPC: G06K15/08 ,  G06F3/12 ,  G06K15/02