-
公开(公告)号：DE3852695D1
公开(公告)日：1995-02-16
申请号：DE3852695
申请日：1988-10-03
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , IRWIN JOHN WILLIAM
Abstract: A multi-processor system includes at lteast a main processor, a co-processor and a video buffer store coupled to accept data from either of the processors for display. In order to maintain a record of data for display from the co-processor when the main processor is controlling the video buffer, a shadow video buffer is provided. This maintains an updated version of display data from the co-processor at all times. When the main processor is controlling the video buffer, the co-processor accesses the shadow buffer. When the co-processor is controlling the video buffer, it updates both the video buffer and the shadow buffer simultaneously.
-
公开(公告)号：DE68921776D1
公开(公告)日：1995-04-27
申请号：DE68921776
申请日：1989-01-05
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN
Abstract: The disclosed arrangement simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by using a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application program instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction and pruning the same from the translation so that fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.
-
公开(公告)号：DE68922321T2
公开(公告)日：1995-11-02
申请号：DE68922321
申请日：1989-01-05
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN , O'QUIN JOHN CLAUDE
-
Patent Agency Ranking
公开(公告)号：DE68921776T2
公开(公告)日：1995-10-12
申请号：DE68921776
申请日：1989-01-05
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN
Abstract: The disclosed arrangement simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by using a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application program instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction and pruning the same from the translation so that fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.
-
公开(公告)号：DE68921775T2
公开(公告)日：1995-10-12
申请号：DE68921775
申请日：1989-01-05
Applicant: IBM
Inventor： BLACKARD JOE WAYNE , FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN
Abstract: The arrangement disclosed simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by using a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions. A method is used to determine at the time of a store to memory whether an instruction, data, or video, is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarnatee the correct execution of the modified instruction. If the simulator determines at the time of a store that the the memory location being modified is data, the simulator needs to take no additional steps.
-
公开(公告)号：DE3852695T2
公开(公告)日：1995-06-29
申请号：DE3852695
申请日：1988-10-03
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , IRWIN JOHN WILLIAM
Abstract: A multi-processor system includes at lteast a main processor, a co-processor and a video buffer store coupled to accept data from either of the processors for display. In order to maintain a record of data for display from the co-processor when the main processor is controlling the video buffer, a shadow video buffer is provided. This maintains an updated version of display data from the co-processor at all times. When the main processor is controlling the video buffer, the co-processor accesses the shadow buffer. When the co-processor is controlling the video buffer, it updates both the video buffer and the shadow buffer simultaneously.
-
公开(公告)号：DE68922321D1
公开(公告)日：1995-06-01
申请号：DE68922321
申请日：1989-01-05
Applicant: IBM
Inventor： FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN , O'QUIN JOHN CLAUDE
-
公开(公告)号：DE68921775D1
公开(公告)日：1995-04-27
申请号：DE68921775
申请日：1989-01-05
Applicant: IBM
Inventor： BLACKARD JOE WAYNE , FOGG RICHARD GREGORY , DE NICOLAS ARTURO MARTIN
Abstract: The arrangement disclosed simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by using a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions. A method is used to determine at the time of a store to memory whether an instruction, data, or video, is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarnatee the correct execution of the modified instruction. If the simulator determines at the time of a store that the the memory location being modified is data, the simulator needs to take no additional steps.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.017 seconds)
