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Patent Agency Ranking
公开(公告)号：US3786434A
公开(公告)日：1974-01-15
申请号：US3786434D
申请日：1972-12-20
Applicant: IBM
Inventor： FRYE H , MC MAHON R
CPC classification number: G06F9/267
Abstract: A microprogrammed control unit comprising an instruction memory for storing microinstructions with no repetitions and an address memory for storing the addresses of microinstructions which make up a microprogram. Within the instruction memory, micro-orders are densely stored. Each time that a word is accessed from the instruction storage, a mask which is stored along with the address in the address storage is utilized to select appropriate micro-orders to produce a desired microinstruction. Through the use of the mask, and associated gates, each word in the instruction storage is capable of supplying a plurality of microinstructions to the system.
Abstract translation: 一种微程序控制单元，包括用于存储不重复的微指令的指令存储器和用于存储构成微程序的微指令的地址的地址存储器。 在指令存储器中，微订单密集存储。 每当从指令存储器访问单词时，利用与地址存储器中的地址一起存储的掩码来选择合适的微命令以产生所需的微指令。 通过使用掩模和相关联的门，指令存储器中的每个字能够向系统提供多个微指令。
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公开(公告)号：SE340710B
公开(公告)日：1971-11-29
申请号：SE1792166
申请日：1966-12-29
Applicant: IBM
Abstract: 1,143,119. Cathode-ray tube displays. INTERNATIONAL BUSINESS MACHINES CORP 20 Oct., 1966 [29 Dec., 1965], No. 46894/66. Heading H4T. In a cathode-ray tube display arrangement binary coded signals representative of Alpha- Numeric &c. characters and produced by a keyboard 10 (Fig. 1) are converted to corresponding video signals by a composer 12 and to corresponding binary-doded-decimal (BCD) signals by a correcter 13, both sets of signals being stored in a cyclical delay line store 21 synchronously with the operation of the display tube 33, the former during time portions corresponding to vertical trace intervals and the latter during time portions corresponding to vertical re-trace intervals. The characters produced may then be verified visually by the operator and after any necessary correction the application of a (positive) pulse to read line 50 supplies the equivalent binary-coded-decimal signals to a load device 42 which may be a data processing system. The delay line 21 stores a complete field of video and BCD signals and in the display each character is allotted a matrix of 6 (wide) by 8 (high) charac - ter bits of which 5 by 7 are utilized for video production whilst the extra bits are employed for horizontal and vertical spacing giving a total of 8 lines each containing 18 characters (Figs. 2 to 7, not shown). In practice; the delay line comprises two delay line elements (Fig. 8, not shown) which receive the odd and even numbered bits respectively, the outputs being fed back to the inputs for recirculation until the feed-back path is interrupted by manually operated switch means when a new set of characters is to be entered into the system. The output of the timing control circuit 54 (described in detail in connection with Fig. 9, not shown) comprising horizontal and vertical synchronizing signals may be combined with video signals from the delay line and fed to the video amplifier of a conventional television receiver used as the display means.
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公开(公告)号：SE340709B
公开(公告)日：1971-11-29
申请号：SE1674266
申请日：1966-12-07
Applicant: IBM
Abstract: 1,143,119. Cathode-ray tube displays. INTERNATIONAL BUSINESS MACHINES CORP 20 Oct., 1966 [29 Dec., 1965], No. 46894/66. Heading H4T. In a cathode-ray tube display arrangement binary coded signals representative of Alpha- Numeric &c. characters and produced by a keyboard 10 (Fig. 1) are converted to corresponding video signals by a composer 12 and to corresponding binary-doded-decimal (BCD) signals by a correcter 13, both sets of signals being stored in a cyclical delay line store 21 synchronously with the operation of the display tube 33, the former during time portions corresponding to vertical trace intervals and the latter during time portions corresponding to vertical re-trace intervals. The characters produced may then be verified visually by the operator and after any necessary correction the application of a (positive) pulse to read line 50 supplies the equivalent binary-coded-decimal signals to a load device 42 which may be a data processing system. The delay line 21 stores a complete field of video and BCD signals and in the display each character is allotted a matrix of 6 (wide) by 8 (high) charac - ter bits of which 5 by 7 are utilized for video production whilst the extra bits are employed for horizontal and vertical spacing giving a total of 8 lines each containing 18 characters (Figs. 2 to 7, not shown). In practice; the delay line comprises two delay line elements (Fig. 8, not shown) which receive the odd and even numbered bits respectively, the outputs being fed back to the inputs for recirculation until the feed-back path is interrupted by manually operated switch means when a new set of characters is to be entered into the system. The output of the timing control circuit 54 (described in detail in connection with Fig. 9, not shown) comprising horizontal and vertical synchronizing signals may be combined with video signals from the delay line and fed to the video amplifier of a conventional television receiver used as the display means.
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