公开(公告)号：JP2000305842A

公开(公告)日：2000-11-02

申请号：JP2000084906

申请日：2000-03-24

Applicant: IBM

Inventor： GARY DEAN ANDERSON ,  ARROYO RONALD XAVIER ,  BRADLEY GEORGE FREY ,  GUY LYNN GUTHRIE

IPC: G06F13/14 ,  G06F12/08 ,  G06F13/28 ,  G06F13/36

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for improving the speed and efficiency of a direct memory access device. SOLUTION: A specific I/O page has a large size and is defined so as to have a distinguishable cache line characteristic. In the case of DMA reading, a 1st cache line in the I/O page 134 can be accessed as a cacheable reading line by a PCI host bridge 108 but all other lines can not be accessed because of cache disabled lines. In the case of DMA writing, the bridge 108 can access all the cache lines as cacheable lines. The bridge 108 manages cache snoop granularity of I/O page size for data, and if detecting store type system bus operation on a cache line in the I/O page, invalidates cached data in the page.