公开(公告)号：GB2579494A

公开(公告)日：2020-06-24

申请号：GB202001857

申请日：2018-06-27

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/08

Abstract: Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply—accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by distributing the synaptic weight across multiple conductances of varying significance, implementing carry operations between less-significant signed analog conductance-pairs to more-significant analog conductance-pairs.

公开(公告)号：IL297331A

公开(公告)日：2022-12-01

申请号：IL29733122

申请日：2022-10-13

Applicant: IBM ,  HSINYU TSAI ,  GEOFFREY BURR ,  PRITISH NARAYANAN

Inventor： HSINYU TSAI ,  GEOFFREY BURR ,  PRITISH NARAYANAN

Abstract: Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.

公开(公告)号：GB2581310B

公开(公告)日：2020-12-09

申请号：GB202008959

申请日：2018-11-19

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/063 ,  G06N3/08

Abstract: Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply—accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by periodically inverting the polarity of less-significant signed analog conductance-pairs within synaptic weights that are distributed across multiple conductances of varying significance, upon transfer of weight information between less-significant signed analog conductance-pairs to more-significant analog conductance-pairs.

公开(公告)号：GB2597000B

公开(公告)日：2022-12-07

申请号：GB202115312

申请日：2020-04-07

Applicant: IBM

Inventor： ESTEBAN AMBROGIO GALI ,  GEOFFREY BURR ,  CHARLES MACKIN ,  SIDNEY TSAI ,  PRITISH NARAYANAN

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

Abstract: A computer implemented method includes updating weight values associated with a plurality of analog synapses in a cross-bar array that implements an artificial neural network by sending a pulse sequence to the analog synapses. Each analog synapse includes a conductance unit, wherein a weight value of the analog synapse is based on a conductance value of the conductance unit. The pulse sequence changes the conductance value. The method further includes comparing the weight values of the analog synapses with target weight values associated with the analog synapses and selecting a set of analog synapses based on the comparison. The method further includes updating the weight values of the selected analog synapses by sending a set of electric pulses of varying durations.

公开(公告)号：GB2600890A

公开(公告)日：2022-05-11

申请号：GB202202192

申请日：2020-07-17

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/08

Abstract: A computer-implemented method for suppressing outlier drift of a phase change memory (PCM) device includes programming, by a controller, a conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first time-point, the first time-point being a programming time-point. The programming further includes determining, at a first pre-compensation time-point, that the conductance of the PCM device has changed to a second conductance value that differs from a target conductance value by no more than a predetermined threshold. Further, the programming includes, based on the above determination, reprogramming the PCM device to the first conductance value at a second time-point, including measuring said pre-compensation again, but at a second pre-compensation time-point.

公开(公告)号：GB2600864A

公开(公告)日：2022-05-11

申请号：GB202201802

申请日：2020-07-17

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/063

Abstract: Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.

公开(公告)号：GB2579494B

公开(公告)日：2022-03-30

申请号：GB202001857

申请日：2018-06-27

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/06 ,  G06N3/08

Abstract: Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply-accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by distributing the synaptic weight across multiple conductances of varying significance, implementing carry operations between less-significant signed analog conductance-pairs to more-significant analog conductance-pairs.

公开(公告)号：GB2597000A

公开(公告)日：2022-01-12

申请号：GB202115312

申请日：2020-04-07

Applicant: IBM

Inventor： ESTEBAN AMBROGIO GALI ,  GEOFFREY BURR ,  CHARLES MACKIN ,  SIDNEY TSAI ,  PRITISH NARAYANAN

IPC: G06N3/06

Abstract: A computer implemented method includes updating weight values associated with a plurality of analog synapses in a cross-bar array that implements an artificial neural network by sending a pulse sequence to the analog synapses. Each analog synapse includes a conductance unit, wherein a weight value of the analog synapse is based on a conductance value of the conductance unit. The pulse sequence changes the conductance value. The method further includes comparing the weight values of the analog synapses with target weight values associated with the analog synapses and selecting a set of analog synapses based on the comparison. The method further includes updating the weight values of the selected analog synapses by sending a set of electric pulses of varying durations.

公开(公告)号：GB2581310A

公开(公告)日：2020-08-12

申请号：GB202008959

申请日：2018-11-19

Applicant: IBM

Inventor： GEOFFREY BURR

IPC: G06N3/063 ,  G06N3/08

Abstract: Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply— accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by periodically inverting the polarity of less-significant signed analog conductance-pairs within synaptic weights that are distributed across multiple conductances of varying significance, upon transfer of weight information between less-significant signed analog conductance-pairs to more-significant analog conductance- pairs.

公开(公告)号：GB2569710A

公开(公告)日：2019-06-26

申请号：GB201903530

申请日：2017-09-21

Applicant: IBM

Inventor： GEOFFREY BURR ,  PRITISH NARAYANAN

IPC: G06N3/04 ,  G06N3/08

Abstract: Single-shot learning and disambiguation of multiple predictions in hierarchical temporal memory is provided. In various embodiments an input sequence is read. The sequence comprises first, second, and third time-ordered components. Each of the time-ordered components is encoded in a sparse distributed representation. The sparse distributed representation of the first time-ordered component is inputted into a first portion of a hierarchical temporal memory. The sparse distributed representation of the second time- ordered component is inputted into a second portion of the hierarchical temporal memory. The second portion is connected to the first portion by a first plurality of synapses. A plurality of predictions as to the third time-ordered component is generated within a third portion of the hierarchical temporal memory. The third portion is connected to the second portion by a second plurality of synapses. Based on the plurality of predictions, additional synaptic connections are added between the first portion and the second portion.