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    Computer-orientated test system having digital measuring means with automatic range-changing feature
    2.
    发明授权
    Computer-orientated test system having digital measuring means with automatic range-changing feature 失效
    具有自动变化特征的数字测量装置的计算机定向测试系统

    公开(公告)号：US3648175A

    公开(公告)日：1972-03-07

    申请号：US3648175D

    申请日：1969-11-20

    Applicant: IBM

    Inventor： BARNARD JOHN D ,  GAITO CARL C ,  GIEDD GARY R ,  GREENE THOMAS G ,  LIND JAMES W ,  PERKINS MERLYN H ,  PROSS CHARLES M

    IPC: G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G01R17/06 ,  G01R15/08

    CPC classification number: G01R31/3193 ,  G01R31/31713 ,  G01R31/31917

    Abstract: A test system is provided for performing functional tests on combinatorial and sequential monolithic devices with the testing automatically programmed under control of a computer processing unit. The test results can be printed out on a printer, logged on tape and/or punched on cards. Tests are performed by the system under the control of an operational test program comprised of a plurality of interrelated subprograms. The operational test program is run by a computer processing unit which processes the programmed instructions through an input-output logic control section which sets up the test circuit configurations in and commands to an analog section. The analog section provides the required bias, pin resistor loads and signal levels to a device under test. The test parameter data is sensed by a digital voltmeter for conversion from analog-todigital data form, and for optional visual display if desired. The digital test parameter data is inserted in a comparator for pass/fail logic comparison. High, Low and/or No-Fail information is added by the comparator and sent with the converted digital information to the input-output logic control section where the data is serialized and fed to the computer processing unit for logging or analysis.

    Random number statistical logic test system
    3.
    发明授权
    Random number statistical logic test system 失效
    随机数统计逻辑测试系统

    公开(公告)号：US3614608A

    公开(公告)日：1971-10-19

    申请号：US3614608D

    申请日：1969-05-19

    Applicant: IBM

    Inventor： GIEDD GARY R ,  MALEY GERALD A ,  PERKINS MERLYN H

    IPC: G06F11/22 ,  G01R31/3183 ,  G01R31/3193 ,  G06F7/58 ,  H03K3/84 ,  G01R15/12

    CPC classification number: G01R31/3193 ,  G01R31/318385

    Abstract: A system for testing complex circuitry primarily in large scale integration, where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a random number generator which simultaneously applies a plurality of signals in a random pattern to the plurality of input pins of both the test circuit and a reference circuit. Compare circuitry is responsive to signals received from the test and reference circuits and provides an error signal when the two outputs are not matched.

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