公开(公告)号：AU2021291706A1

公开(公告)日：2022-11-10

申请号：AU2021291706

申请日：2021-06-16

Applicant: IBM

Inventor： LIU YANG ,  XU YUE ,  GOU PENG FEI ,  LI MENG ,  ZHAO XING

IPC: G06F11/34

Abstract: A method comprises receiving a workload for a computer system; sweeping at least one parameter of the computer system while executing the workload; monitoring one or more characteristics of the computer system while sweeping the at least one parameter, the one or more characteristics including total power consumption of the computer system; generating a power profile for the workload that indicates a respective selected value for the at least one parameter based on analysis of the monitored total power consumption of the computer system while sweeping the at least one parameter, and executing the workload based on the respective selected value of the at least one parameter.

公开(公告)号：GB2519545A

公开(公告)日：2015-04-29

申请号：GB201318775

申请日：2013-10-24

Applicant: IBM

Inventor： HOOPE BODO ,  GOU PENG FEI ,  LIU DAN ,  PAN YONG FENG

IPC: G06F17/50

Abstract: A method for determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. The method comprises generating a netlist from the hardware design language description 102, generating a list of hardware design outputs 104, and generating logical paths in the netlist 106 based on the list of hardware design outputs. Furthermore, the method comprises generating a modified netlist 108 involving logical paths by determining whether a gate is selected as an insertion point 110, and selecting a fault type for the selected gate in the netlist 112 and inserting a mutant and associated activation and monitoring logic in the netlist. The fault type, mutant and associated monitoring logic are selected from a mutant database. A fault simulation is then performed 114 and the quality parameter is determined for the verification environment 116 from the fault simulation and the simulation result data. Selecting gates as insertion points may comprise generating an efficiency vector for components of the logical path. The efficiency vector may comprise identifiers for an insertion point, a fault type and/or a mutant type.